Download SD57120

SD57120
RF power transistor
the LdmoST family
Features
■
Excellent thermal stability
■
Common source configuration push-pull
■
POUT = 120W with 13dB gain @ 960MHz
■
BeO free package
■
Internal input matching
■
In compliance with the 2002/95/EC european
directive
M252
Epoxy sealed
Description
The SD57120 is a common source N-channel
enhancement-mode lateral Field-Effect RF power
transistor designed for broadband commercial
and industrial applications at frequencies up to
1.0 GHz. The SD57120 is designed for high gain
and broadband performance operating in
common source mode at 28V. Its internal
matching makes it ideal for base station
applications requiring high linearity.
Figure 1.
Pin connection
1
2
5
4
3
1. Drain
4. Gate
2. Drain
5. Gate
3. Source
Table 1.
August 2007
Device summary
Order code
Package
Branding
SD57120
M252
SD57120
Rev 8
1/13
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13
Contents
SD57120
Contents
1
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Static . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Dynamic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Typical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Text circuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2/13
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SD57120
Electrical data
1
Electrical data
1.1
Maximum ratings
Table 2.
Absolute maximum ratings (TCASE = 25°C)
Symbol
Value
Unit
V(BR)DSS
Drain-source voltage
65
V
VGS
Gate-source voltage
± 20
V
Drain current
14
A
Power dissipation (@ Tc = 70°C)
236
W
Max. operating junction temperature
200
°C
-65 to + 150
°C
Value
Unit
0.55
°C/W
ID
PDISS
TJ
TSTG
1.2
Parameter
Storage temperature
Thermal data
Table 3.
Symbol
RthJC
Thermal data
Parameter
Junction - case thermal resistance
3/13
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Electrical characteristics
2
SD57120
Electrical characteristics
TCASE = +25 oC
2.1
Static
Table 4.
Static
Symbol
Test conditions
Min
Typ
Max
Unit
V(BR)DSS
VGS = 0 V
IDS = 1 mA
IDSS
VGS = 0 V
VDS = 28 V
1
µA
IGSS
VGS = 20 V
VDS = 0 V
1
µA
VGS(Q)
VDS = 28 V
ID = 100 mA
5.0
V
VDS(ON)
VGS = 10 V
ID = 3 A
0.7
0.9
V
GFS
VDS = 10 V
ID = 3 A
3
S
CISS(1)
VGS = 0 V
VDS = 28 V
f = 1 MHz
169
pF
COSS
VGS = 0 V
VDS = 28 V
f = 1 MHz
48
pF
CRSS
VGS = 0 V
VDS = 28 V
f = 1 MHz
2.7
pF
65
V
2.0
1. Includes Internal Input Moscap.
2.2
Dynamic
Table 5.
Dynamic
Symbol
Test conditions
Min
Typ
Max
Unit
POUT
VDD = 28 V
IDQ = 800 mA
f = 960MHz
120
GPS
VDD = 28 V
IDQ = 800 mA
POUT = 120W f = 960MHz
13
hD
VDD = 28 V
IDQ = 800 mA
POUT = 120W f = 960MHz
50
%
Load
VDD = 28 V IDQ = 800 mA
mismatch All phase angles
POUT = 120W f = 960MHz
10:1
VSW
R
4/13
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W
14
dB
SD57120
3
Note:
Impedance
Impedance
Figure 2.
Current conventions
Table 6.
Impedance data
Freq. (MHz)
ZIN (Ω)
ZDL(Ω)
945 MHz
3.9 + j 4.9
3.26 - j 5.1
960 MHz
4.1 + j 4.6
3.24 - j 4.74
980 MHz
3.9 + j 5.2
3.27 - j 6.9
Measured gateto gate and drain to drain respectively.
5/13
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Typical performance
SD57120
4
Typical performance
Figure 3.
Output power and efficiency vs
input power
160
70
Nd
100
50
80
40
60
30
40
20
f= 960MHz
Idq= 800mA
Vdd= 28V
20
17
Idq= 1200mA
Gp, POWER GAIN (dB)
60
Nd, DRAIN EFFICIENCY (%)
120
2
3
4
5
6
7
15
Idq= 400mA
14
Idq= 200mA
8
12
1
9
10
Table 7.
-25
IMD3, INTERMODULATION DISTORSION (dBc)
IMD, INTERMODULATION DISTORSION (dBc)
Intermodulation distortion vs
output power
Vdd= 28V
Idq= 800mA
f1= 960MHz
f2= 960.1MHz
Pin= 2.5WPEP
-30
IMD3
-35
IMD5
-40
-45
IMD7
-50
-55
10
100
Pout, OUTPUT POWER (WPEP)
100
1000
Pout, OUTPUT POWER (W)
Pin, INPUT POWER (W)
Figure 5.
f= 960MHz
Vdd= 28V
Idq= 800mA
13
0
1
16
10
0
0
Power gain vs output power
18
80
Pout
140
Pout, OUTPUT POWER (W)
Figure 4.
1000
Intermodulation distortion vs
output power
-25
Vdd= 28V
Idq= 800mA
f1= 960MHz
f2= 960.1MHz
Pin= 2.5WPEP
Idq= 200mA
-30
Idq= 1200mA
-35
-40
Idq= 400mA
Idq= 800mA
-45
10
100
Pout, OUTPUT POWER (WPEP)
6/13
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1000
SD57120
Table 8.
Typical performance
Output power vs gate voltage
Figure 6.
160
Output power vs drain voltage
200
Pin= 6W
Pout, OUTPUT POWER (W)
Pout, OUTPUT POWER (W)
140
120
100
80
f= 960MHz
Pin= 4.8W
Vdd= 28V
60
f= 960MHz
Idq= 800mA
150
Pin= 4.8W
100
Pin= 2.4W
50
40
0
1
2
3
4
5
6
0
Vgs, GATE-SOURCE VOLTAGE (V)
10
15
20
25
30
35
Vdd, DRAIN VOLTAGE (V)
Figure 7.
Capacitance vs drain voltage
Figure 8.
9
1000
f= 1MHz
8
Vds= 10V
Ciss
100
7
Id, DRAIN CURRENT (A)
C, CAPACITANCE (pF)
Drain current vs gate voltage
Coss
10
Crss
6
5
4
3
2
1
Ciss includesinput matching capacitors
0
1
0
4
8
12
16
20
Vds, DRAIN SOURCE VOLTAGE (V)
24
28
0
1
2
3
4
5
6
Vgs, GATE-SOURCE VOLTAGE (V)
7/13
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Test circuit
SD57120
5
Test circuit
Figure 9.
960MHz test circuit schematic
Dimensions
TL1
TL2
Z7
Z3
Z9
Z12
Z1
Z10
Z4
Z6
Z8
TRANSMISSON LINE DIMENSIONS
VGG
+
R6 FB4
R5
WxL (in)
WxL (mm)
Z1, Z12
0.084xTYP
2.13xTYP
Z2, Z3
0.250x0.400
6.34x10.16
Z4, Z5
0.250x0.450
6.34x11.43
Z6, Z7
0.450x0.608
11.43x15.44
Z8, Z9
0.430x0.801
10.92x20.34
Z10, Z11
0.252x0.525
6.40x13.34
TL1, TL2
0.084x2.2
2.13x55.88
Z11
Z5
Z2
DIM
C22
C23
VDD
FB6
FB3
C21
C20
C30
C32
C31
L2
C33
BALUN2
C7
TL1
RF
INPUT
Z11 C15
Z9
R2
Z3
Z5
Z7
C4
C5
Z1
Z2 C3
C1
Z4
R1
C10
D.U.T.
Z12
RF
OUTPUT
Z10 C14
TL2
C8
FB1
C19
C13
L3
FB2
R3
C12
Z8
C6
BALUN1
R4
C11
Z6
L1
VGG
+
C35
L4
C9
C2
C34
C18
VDD
FB5
C17
C16
C24
C25
C26
C27
C28
C29
1
Dimensions at component symbols are reference for component placement.
2
Gap between ground & transmission line = 0.056 [1.42] +0.002 [0.05] -0.000 [0.00] typ.
3
Dimension of microstrip = 1/2 printed balun only.
8/13
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SD57120
Test circuit
Table 9.
Test circuit component part list
Component
BF1-BF4
L1,L2,L3,L4
Description
SURFACE MOUNT EMI SHIELD BEAD
INDUCTOR, 3 TURN AIR-WOUND #20AWG ID=0.126[3.20] 24.7nH
MAGNET WIRE
B1, B2
BALUN, 50 OHM SUCOFORM, OD 0.141. 2.20 LG COAXIAL CABLE OR
EQUIVALENT
R1,R2
75 OHM 1 W SURFACE MOUNT CHIP RESISTOR
R3,R5
1.2 K OHM 1 W SURFACE MOUNT CHIP RESISTOR
R4,R6
1 K OHM 1 W SURFACE MOUNT CHIP RESISTOR
C1,C2,C14,C15
47 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C3,C4
42 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C5,C12
0.8-8 pF GIGATRIM VARIABLE CAPACITOR
C6,C7,C11
1.7 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C8,C9
5.6 pF ATC 100B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C10,C13
0.6-4.5 pF GIGATRIM VARIABLE CAPACITOR
C16,C17,C20,C21,
300 pF ATC 700B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C24,C25,C30,C31
C18,C22
10000 pF ATC 200B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C19,C23,C27,C28,
10 µF, 50 V ALUMINUM ELECTROLYTICS RADIAL LEAD CAPACITOR
C32,C34
C26,C33
20000 pF ATC 900B SURFACE MOUNT CERAMIC CHIP CAPACITOR
C29,C35
220 µF, 50 V ALUMINUM ELECTROLYTICS RADIAL LEAD CAPACITOR
BOARD
ULTRA LAM 2000. 0.030” THK, εr = 2.55, 2 OZ ED CU BOTH SIDES
9/13
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Text circuit layout
6
SD57120
Text circuit layout
Figure 10. 960MHz production test fixture
4 inches
Figure 11. 960MHz test circuit photomaster
6.4 inches
10/13
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SD57120
7
Package mechanical data
Package mechanical data
Table 10.
M252 (.400 x .860 4L BAL N/HERM W/FLG) mechanical data
Dim.
mm.
Min
A
Typ
8.13
B
Inch
Max
Min
8.64
.320
10.80
Typ
Max
.340
.425
C
3.00
3.30
.118
.130
D
9.65
9.91
.380
.390
E
2.16
2.92
.085
.115
F
21.97
22.23
.865
.875
G
27.94
1.100
H
33.91
34.16
1.335
1.345
I
0.10
0.15
.004
.006
J
1.52
1.78
.060
.070
K
2.36
2.74
.093
.108
L
4.57
5.33
.180
.210
M
9.96
10.34
.392
.407
N
21.64
22.05
.852
.868
Figure 12. Package dimensions
Controlling dimension: Inches
1022783C
11/13
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Revision history
8
SD57120
Revision history
Table 11.
Document revision history
Date
Revision
Changes
24-Mar-2003
6
First Issue.
11-Jul-2007
7
Document reformatted, added lead free info
27-Aug-2007
8
Cover page title updated
12/13
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SD57120
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