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MITSUBISHI MITSUBISHI SEMICONDUCTOR SEMICONDUCTOR <Intelligent <Intelligent Power Power Module> Module> PS21255-E PS21255-E TRANSFER-MOLD TRANSFER-MOLD TYPE TYPE INSULATED INSULATED TYPE TYPE PS21255-E INTEGRATED POWER FUNCTIONS 4th generation (planar) IGBT inverter bridge for 3 phase DC-to-AC power conversion. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS • For upper-leg IGBTS : Drive circuit, High voltage isolated high-speed level shifting, Control circuit under-voltage (UV) protection. Note : Bootstrap supply scheme can be applied. • For lower-leg IGBTS : Drive circuit, Control circuit under-voltage protection (UV), Short circuit protection (SC). • Fault signaling : Corresponding to a SC fault (Low-side IGBT) or a UV fault (Low-side supply). • Input interface : 5V line CMOS/TTL compatible, Schmitt Trigger receiver circuit. APPLICATION AC100V~200V three-phase inverter drive for small power motor control. Fig. 1 PACKAGE OUTLINES Dimensions in mm 27×2.8(=75.6) TERMINAL CODE 12 13 14 15 16 17 18 19 20 21 24 25 26 A 10±0.3 10±0.3 10±0.3 20±0.3 3.8±0.2 14 15 16 17 18 19 20 21 22 23 24 25 26 VN1 VNC CIN CFO FO UN VN WN P U V W N 0.5±0.2 (71) HEAT SINK SIDE Detail A 1.9±0.05 1±0.2 3.25MAX Detail B (t=0.7) 1.75MAX 0.8±0.2 0.6±0.5 C 8±0.5 B Irrgulor solder remains 0.5MAX 79±0.5 Irrgulor solder remains 0.5MAX 67±0.3 0.6±0.5 23 UP VP1 VUFB VUFS VP VP1 VVFB VVFS WP VP1 VPC VWFB VWFS 45° 22 11.5±0.5 Type name , Lot No. .2 ±0 4.5 2-φ 1 2 3 4 5 6 7 8 9 10 11 12 13 28±0.5 9 10 11 21.4±0.5 7 8 31±0.5 5 6 13.4±0.5 3 4 16±1 or 12.8±1 1 2 3~5° 2.8±0.3 Detail C (t=0.7) Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE) CBW– CBW+ CBU+ CBV+ CBV– CBU– High-side input (PWM) (5V line) (Note 1,2) C3 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance value depends on the PWM control scheme used in the applied system). C4 : 0.22~2µF R-category ceramic capacitor for noise filtering. Bootstrap circuit C4 C3 Input signal Input signal Input signal coditioning coditioning coditioning For detailed description of the boot-strap circuit construction, please contact Mitsubishi Electric Level shifter Level shifter Level shifter Protection circuit (UV) Protection circuit (UV) (Note 6) Protection circuit (UV) DIP-IPM Drive circuit Drive circuit Drive circuit Inrush current limiter circuit P AC line input H-side IGBTS (Note 4) C Fig. 3 U V W M AC line output Z N1 VNC Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Note : Additionally, an appropriate line-to line surge absorber circuit may become necessary depending on the application environment). N L-side IGBTS CIN Drive circuit Protection circuit Fo logic Input signal conditioning Control supply Under-Voltage protection FO CFO Low-side input (PWM) (5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5) Note1: 2: 3: 4: 5: 6: VNC VD (15V line) To prevent the input signals oscillation, an RC coupling at each input is recommended. (see also Fig. 6) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. (see also Fig. 6) This output is open collector type. The signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig. 6) The wiring between the power DC link capacitor and the P/N1 terminals should be as short as possible to protect the DIP-IPM against catastrophic high surge voltages. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N1 DC power input pins. Fo output pulse width should be decided by putting external capacitor between CFO and VNC terminals. (Example : CFO=22nF → tFO=1.8ms (Typ.)) High voltage (600V or more) and fast recovery type (less than 100ns) diodes should be used in the bootstrap circuit. Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT DIP-IPM Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) after allowing a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system when the Fo signal is received and check the fault. Drive circuit P IC (A) H-side IGBTS SC Protection Trip Level U V W L-side IGBTS External protection circuit N1 Shunt Resistor A N (Note 1) VNC C R Drive circuit CIN B C Collector current waveform Protection circuit 0 (Note 2) Note1: In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0µs. 2: To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible. 2 tw (µs) Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE MAXIMUM RATINGS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol VCC VCC(surge) VCES ±IC ±ICP PC Tj Parameter Condition Applied between P-N Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Ratings Applied between P-N TC = 25°C TC = 25°C, instantaneous value (pulse) TC = 25°C, per 1 chip (Note 1) 450 500 600 20 40 56 –20~+150 Unit V V V A A W °C Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150°C (@ TC ≤ 100°C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) ≤ 125°C (@ TC ≤ 100°C). CONTROL (PROTECTION) PART Symbol VD Parameter Control supply voltage Condition Applied between VP1-VPC, VN1-VNC VDB Control supply voltage VCIN Input voltage VFO Fault output supply voltage Fault output current Current sensing input voltage Applied between VUFB-VUFS, VVFB-VVFS , VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, W N-VNC Applied between F O-VNC Sink current at F O terminal Applied between CIN-V NC IFO VSC Ratings 20 Unit V 20 V –0.5~+5.5 V –0.5~VD+0.5 15 –0.5~VD+0.5 V mA V Ratings Unit 400 V –20~+100 –40~+125 °C °C 1500 Vrms TOTAL SYSTEM Symbol Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso Isolation voltage Condition VD = 13.5~16.5V, Inverter part Tj = 125°C, non-repetitive, less than 2 µs (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Note 2 : T C MEASUREMENT POINT Control Terminals DIP-IPM Heat sink boundary Heat sink Tc Tc Power Terminals Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE THERMAL RESISTANCE Symbol Parameter Rth(j-c)Q Rth(j-c)F Junction to case thermal resistance Rth(c-f) Contact thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWD part (per 1/6 module) Case to fin, (per 1 module) thermal grease applied Limits Unit Min. Typ. Max. — — — — 2.2 4.5 °C/W °C/W — — 0.067 °C/W Limits Typ. Max. 1.80 1.90 2.20 0.80 0.10 0.50 0.80 0.40 — — 2.45 2.60 3.00 1.30 — 0.90 1.90 1.30 1 10 ELECTRICAL CHARACTERISTICS (Tj = 25°C, unless otherwise noted) INVERTER PART Symbol Parameter VCE(sat) Collector-emitter saturation voltage VEC ton trr tc(on) toff tc(off) FWD forward voltage ICES Collector-emitter cut-off current Switching times Condition IC = 20A, Tj = 25°C VD = VDB = 15V VCIN = 0V IC = 20A, Tj = 125°C Tj = 25°C, –IC = 20A, VCIN = 5V VCC = 300V, VD = VDB = 15V IC = 20A, Tj = 125°C, V CIN = 5V ↔ 0V Inductive load (upper-lower arm) VCE = VCES Tj = 25°C Tj = 125°C Min. — — — 0.10 — — — — — — Unit V V µs µs µs µs µs mA CONTROL (PROTECTION) PART Symbol Parameter VD VDB Control supply voltage Control supply voltage ID Circuit current VFOH VFOL VFOsat Fault output voltage tdead Arm shoot-through blocking time Condition Applied between VP1-VPC, VN1 -VNC Applied between VUFB-VUFS, VVFB-VVFS , VWFB-VWFS VD = V DB = 15V, Total of VP1-VPC, VN1 -VNC VCIN= 5V VUFB-VUFS, VVFB -VVFS , VWFB-VWFS VSC = 0V, FO = 10kΩ 5V pull-up VSC = 1V, FO = 10kΩ 5V pull-up VSC = 1V, IFO = 15mA Relates to corresponding input signal for blocking arm shoot-through. –20°C ≤ TC ≤ 100°C Limits Min. 13.5 13.5 — — 4.9 — 0.8 Typ. 15.0 15.0 — — — 0.8 1.2 Max. 16.5 16.5 8.50 1.00 — 1.2 1.8 2.5 — — Unit V V mA V V V µs Tj = 25°C, VD = 15V Short circuit trip level (Note 3) V VSC(ref) 0.5 0.45 0.55 Trip level V UVDBt — 10.0 12.0 Reset level Supply circuit under-voltage UVDBr — 10.5 12.5 V T j ≤ 125°C protection Trip level UVDt — 10.3 12.5 V Reset level — 10.8 13.0 UVDr V CFO = 22nF (Note 4) Fault output pulse width 1.8 1.0 — tFO ms 1.4 0.8 2.0 ON threshold voltage Vth(on) V Applied between : UP, VP, WP-VPC, UN, VN, WN-VNC OFF threshold voltage 3.0 2.5 4.0 V Vth(off) Note 3 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 34 A. 4 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 12.2 ✕ 10-6 ✕ tFO [F]. Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE MECHANICAL CHARACTERISTICS AND RATINGS Limits Condition Parameter Mounting torque Terminal pulling strength Bending strength Weight Heat-sink flatness Mounting screw : M4 Weight 19.6N Weight 9.8N. 90deg bend — EIAJ-ED-4701 EIAJ-ED-4701 — — (Note 5) Min. 0.98 10 2 — –50 Typ. 1.18 — — 54 — Max. 1.47 — — — 100 Limits Typ. Max. Unit N·m s times g µm Note 5: Measurement point of heat-sink flatness (Note 5) DIP-IPM Measurement point 3mm Place to contact a heat sink Heat sink Heat sink RECOMMENDED OPERATION CONDITIONS Symbol Parameter VCC VD VDB ∆VD, ∆VDB tdead fPWM VCIN(ON) VCIN(OFF) Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Input ON threshold voltage Input OFF threshold voltage Condition Applied between P-N Applied between V P1-VPC, V N1-VNC Applied between V UFB-VUFS, VVFB -VVFS, V WFB-VWFS Relates to corresponding input signal for blocking arm shoot-through T C ≤ 100°C, Tj ≤ 125°C Applied between UP, VP, WP-VPC Applied between U N, V N, WN-VNC Min. 0 13.5 13.5 –1 2.5 — 300 15.0 15.0 — — 15 0~0.65 4.0~5.5 400 16.5 16.5 1 — — Unit V V V V/µs µs kHz V V Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE Fig. 4 THE DIP-IPM INTERNAL CIRCUIT DIP-IPM VUFB VUFS VP1 UP P HVIC 1 VB VCC IGBT1 Di1 HO IN VS COM U VVFB VVFS VP1 VP HVIC 2 VB VCC Di2 IGBT2 HO IN VS COM V VWFB VWFS HVIC 3 VP1 VCC WP IN VPC COM VB Di3 IGBT3 HO VS W IGBT4 LVIC Di4 UOUT VN1 VCC IGBT5 Di5 VOUT UN UN VN VN WN WN Fo Fo IGBT6 Di6 WOUT VNO CIN VNC GND N CFO CFO CIN Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (N-side only) (For the external shunt resistor and CR connection.) a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. Hard IGBT gate interrupt. a4. IGBT turns OFF. a5. FO timer operation starts : The pulse width of the F O signal is set by the external capacitor CFO. a6. Input “H” : IGBT OFF state. a7. Input “L” : IGBT ON state. a8. IGBT OFF state. N-side control input a6 Protection circuit state a7 SET Internal IGBT gate RESET a3 a2 SC a4 a1 Output current Ic(A) a8 SC reference voltage Sense voltage of the shunt resistor CR circuit time constant DELAY Error output Fo a5 [B] Under-Voltage Protection (N-side, UVD) a1. Normal operation : IGBT ON and carrying current. a2. Under voltage trip (UVDt). a3. IGBT OFF in spite of control input condition. a4. FO timer operation starts. a5. Under voltage reset (UVDr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state Control supply voltage VD SET RESET UVDr UVDt a5 a2 a1 a3 a6 Output current Ic(A) Error output Fo a4 Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE [C] Under-Voltage Protection (P-side, UVDB) a1. Control supply voltage rises : After the voltage level reachs UVDBr, the circuits start to operate when the next input is applied. a2. Normal operation : IGBT ON and carrying current. a3. Under voltage trip (UVDBt). a4. IGBT OFF in spite of control input condition, but there is no FO signal output. a5. Under-voltage reset (UVDBr). a6. Normal operation : IGBT ON and carrying current. Control input Protection circuit state RESET SET RESET UVDBr Control supply voltage VDB a1 UVDBt a2 a5 a3 a4 a6 Output current Ic(A) High-level (no fault output) Error output Fo Fig. 6 RECOMMENDED CPU I/O INTERFACE CIRCUIT 5V line DIP-IPM 5.1kΩ 4.7kΩ UP,VP,WP,UN,VN,WN CPU Fo 1nF 1nF VPC, VNC(Logic) Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and on the wiring impedances of the application’s printed circuit board. Sep. 2001 http://www.BDTIC.com/MITSUBISHI MITSUBISHI SEMICONDUCTOR <Intelligent Power Module> PS21255-E TRANSFER-MOLD TYPE INSULATED TYPE Fig. 7 TYPICAL DIP-IPM APPLICATION CIRCUIT EXAMPLE C1: Tight tolerance temp - compensated electrolytic type; C2,C3: 0.22~2 µ F R-category ceramic capacitor for noise filtering 5V line C2 VUFB C1 VUFS DIP-IPM P VP1 C3 UP VCC VB IN HO COM VS VCC VB C2 U VVFB C1 VVFS VP1 C3 VP IN HO COM VS VCC VB IN HO C2 V M VWFB C1 C P U VWFS VP1 C3 WP VPC U N I T COM W VS UOUT C3 VN1 VCC 5V line VOUT UN VN WN Fo UN VN WOUT If this wiring is too long, short circuit might be caused. WN Fo VNO CIN VNC GND N CFO C CFO CIN C4(CFO ) 15V line A The long wiring of GND might generate noise on input signals and cause IGBT to be malfunctioned. B R1 C5 If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction. Shunt resistor N1 Note 1 : To prevent the input signals oscillation, an RC coupling at each input is recommended, and the wiring of each input should be as short as possible. (Less than 2cm) 2 : By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3 : FO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 5.1kΩ resistance. 4 : FO output pulse width should be decided by connecting an external capacitor between CFO and VNC terminals (C FO). (Example : CFO = 22 nF → tFO = 1.8 ms (typ.)) 5 : Each input signal line should be pulled up to the 5V power supply with approximately 4.7kΩ resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedances of the system’s printed circuit board). Approximately a 0.22~2µF by-pass capacitor should be used across each power supply connection terminals. 6 : To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. 7 : In the recommended protection circuit, please select the R1C5 time constant in the range 1.5~2µs. 8 : Each capacitor should be put as nearby the pins of the DIP-IPM as possible. 9 : To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 pins should be as short as possible. Approximately a 0.1~0.22µF snubber capacitor between the P&N1 pins is recommended. Sep. 2001 http://www.BDTIC.com/MITSUBISHI