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Introduction to CMOS VLSI Design Lecture 18: Design for Low Power Credits: David Harris Harvey Mudd College (Material taken/adapted from Harris’ lecture notes) Outline Power and Energy Dynamic Power Static Power Low Power Design 18: Design for Low Power CMOS VLSI Design Slide 2 Power and Energy Power is drawn from a voltage source attached to the VDD pin(s) of a chip. Instantaneous Power: P(t ) iDD (t )VDD Energy: Average Power: 18: Design for Low Power T T 0 0 E P(t )dt iDD (t )VDDdt T E 1 Pavg iDD (t )VDDdt T T0 CMOS VLSI Design Slide 3 Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CVDD is required On falling output, charge is dumped to GND VDD This repeats Tfsw times iDD(t) over an interval of T fsw 18: Design for Low Power CMOS VLSI Design C Slide 4 Dynamic Power Cont. Pdynamic VDD iDD(t) fsw 18: Design for Low Power CMOS VLSI Design C Slide 5 Dynamic Power Cont. T Pdynamic 1 iDD (t )VDD dt T 0 T VDD iDD (t )dt T 0 VDD TfswCVDD T CVDD 2 f sw VDD iDD(t) fsw 18: Design for Low Power CMOS VLSI Design C Slide 6 Activity Factor Suppose the system clock frequency = f Let fsw = af, where a = activity factor – If the signal is a clock, a = 1 – If the signal switches once per cycle, a = ½ – Dynamic gates: • Switch either 0 or 2 times per cycle, a = ½ – Static gates: • Depends on design, but typically a = 0.1 Dynamic power: Pdynamic aCVDD 2 f 18: Design for Low Power CMOS VLSI Design Slide 7 Short Circuit Current When transistors switch, both nMOS and pMOS networks may be momentarily ON at once Leads to a blip of “short circuit” current. < 10% of dynamic power if rise/fall times are comparable for input and output 18: Design for Low Power CMOS VLSI Design Slide 8 Example 200 Mtransistor chip – 20M logic transistors • Average width: 12 l – 180M memory transistors • Average width: 4 l – 1.2 V 100 nm process – Cg = 2 fF/mm 18: Design for Low Power CMOS VLSI Design Slide 9 Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance and short-circuit current. 18: Design for Low Power CMOS VLSI Design Slide 10 Dynamic Example Static CMOS logic gates: activity factor = 0.1 Memory arrays: activity factor = 0.05 (many banks!) Estimate dynamic power consumption per MHz. Neglect wire capacitance. Clogic 20 106 12l 0.05mm / l 2 fF / mm 24nF Cmem 180 106 4l 0.05mm / l 2 fF / mm 72nF Pdynamic 0.1Clogic 0.05Cmem 1.2 f 8.6 mW/MHz 2 18: Design for Low Power CMOS VLSI Design Slide 11 Static Power Static power is consumed even when chip is quiescent. – Ratioed circuits burn power in fight between ON transistors – Leakage draws power from nominally OFF devices Vgs Vt I ds I ds 0e nvT Vds vT 1 e Vt Vt 0 Vds 18: Design for Low Power s Vsb s CMOS VLSI Design Slide 12 Ratio Example The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high Find static power drawn by the ROM – b = 75 mA/V2 – Vtp = -0.4V 18: Design for Low Power CMOS VLSI Design Slide 13 Ratio Example The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high Find static power drawn by the ROM – b = 75 mA/V2 – Vtp = -0.4V 2 Solution: VDD Vtp I pull-up b 2 24μA Ppull-up VDD I pull-up 29μW Pstatic (31 24) Ppull-up 1.6 mW 18: Design for Low Power CMOS VLSI Design Slide 14 Leakage Example The process has two threshold voltages and two oxide thicknesses. Subthreshold leakage: – 20 nA/mm for low Vt – 0.02 nA/mm for high Vt Gate leakage: – 3 nA/mm for thin oxide – 0.002 nA/mm for thick oxide Memories use low-leakage transistors everywhere Gates use low-leakage transistors on 80% of logic 18: Design for Low Power CMOS VLSI Design Slide 15 Leakage Example Cont. Estimate static power: 18: Design for Low Power CMOS VLSI Design Slide 16 Leakage Example Cont. Estimate static power: 6 6 – High leakage: 20 10 0.2 12l 0.05mm / l 2.4 10 mm – Low leakage: 20 106 0.812l 0.05mm / l 180 106 4l 0.05mm / l 45.6 106 mm I static 2.4 106 m m 20nA / m m / 2 3nA / mm 45.6 10 mm 0.02nA / mm / 2 0.002nA / mm 6 Pstatic 32mA I staticVDD 38mW 18: Design for Low Power CMOS VLSI Design Slide 17 Leakage Example Cont. Estimate static power: 6 6 – High leakage: 20 10 0.2 12l 0.05mm / l 2.4 10 mm – Low leakage: 20 106 0.812l 0.05mm / l 180 106 4l 0.05mm / l 45.6 106 mm I static 2.4 106 m m 20nA / m m / 2 3nA / mm 45.6 10 mm 0.02nA / mm / 2 0.002nA / mm 6 Pstatic 32mA I staticVDD 38mW If no low leakage devices, Pstatic = 749 mW (!) 18: Design for Low Power CMOS VLSI Design Slide 18 Low Power Design Reduce dynamic power – a: – C: – VDD: – f: Reduce static power 18: Design for Low Power CMOS VLSI Design Slide 19 Low Power Design Reduce dynamic power – a: clock gating, sleep mode – C: – VDD: – f: Reduce static power 18: Design for Low Power CMOS VLSI Design Slide 20 Low Power Design Reduce dynamic power – a: clock gating, sleep mode – C: small transistors (esp. on clock), short wires – VDD: – f: Reduce static power 18: Design for Low Power CMOS VLSI Design Slide 21 Low Power Design Reduce dynamic power – a: clock gating, sleep mode – C: small transistors (esp. on clock), short wires – VDD: lowest suitable voltage – f: Reduce static power 18: Design for Low Power CMOS VLSI Design Slide 22 Low Power Design Reduce dynamic power – a: clock gating, sleep mode – C: small transistors (esp. on clock), short wires – VDD: lowest suitable voltage – f: lowest suitable frequency Reduce static power 18: Design for Low Power CMOS VLSI Design Slide 23 Low Power Design Reduce dynamic power – a: clock gating, sleep mode – C: small transistors (esp. on clock), short wires – VDD: lowest suitable voltage – f: lowest suitable frequency Reduce static power – Selectively use ratioed circuits – Selectively use low Vt devices – Leakage reduction: stacked devices, body bias, low temperature 18: Design for Low Power CMOS VLSI Design Slide 24