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TS5V522C
SCDS317 – MARCH 2011
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5V, 5-BITS VIDEO EXCHANGE SWITCH FOR DUAL VGA SOURCE TO SINK -2V
UNDERSHOOT PROTECTION WITH LOW ON-STATE RESISTANCE
Check for Samples: TS5V522C
FEATURES
APPLICATIONS
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Bidirectional Data Flow, With Near-Zero
Propagation Delay
High Bandwidth, 380MHZ (typ) RGB Switching
Low ON-State Resistance (ron) Characteristics
(ron =3 Ω Typical)
Low Input/Output Capacitance Minimizes
Loading and Signal Distortion (CIO(OFF) = 8pF
Typical)
Undershoot Clamp Diodes on Data and
Control Inputs.
Low Power Consumption (Icc = 3uA Max.)
Vcc Operation Range from 4V to 5.5V
Data I/Os Support 0 to 5-V Signaling Levels
(0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V, 4V)
Allow to pull up resistor up to 5V on the I/O
Ioff Supports Live Insertion, Partial Power
Down Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100Ma Per
JESD 78, Class II.
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Digital and Analog Signal Interface
Audio and Video Signal Interface
High Speed Signal Bus Exchange
Bus Isolation, Interleaving
Notebook Computer Graphics Control
OE
AR
1R
2R
BR
AG
1G
2G
BG
AB
1B
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
BSCL
2SCL
1SCL
ASCL
BSCA
2SCA
1SCA
ASCA
BB
2B
SEL
DESCRIPTION
The TS5V522C is high bandwidth analog switches offering a 2:2 dual-graphics crossover solution for VGA signal
switching. The device is designed for switching between 2 VGA sources to either of the two destinations within a
laptop computer. The TS5V522C integrates 5 very high-frequency 380Mhz (typ) SPDT switches for RGB signals,
2 pairs of level-translating buffer for the HSYNC and VSYNC lines, and integrated ESD protection. The 5
crossover switches can be controlled by either 5V or 3.3V TTL control signals.
The TS5V522C would bypass the VGA analog signal to destination with less distortions. DDC Channel (SCA,
SCL) may require to +5Vopen drain level at the VGA connector and it may require a pull up resistor on the
destination side. Active undershoot-protection circuitry on the data ports of the TS5V522C provide protection for
undershoots up to -2V by sensing an undershoot event and ensuring that the switch remains in the proper off
state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
TS5V522C
SCDS317 – MARCH 2011
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
ORDERABLE PART
NUMBER
TOP-SIDE MARKING
SSOP (QSOP) – DBQ
Tape and Reel
TS5V522CDBQR
TS5V522C
TSSOP – PW
Tape and Reel
TS5V522CPWR
TE522C
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Table 1. FUNCTION TABLE
CONTROL
INPUT/OUTPUTS
FUNCTIONS
OE
SEL
1X
2X
L
L
AX
BX
1X port = AX port
2x port = BX port
L
H
BX
AX
1X port = BX port
2x port = AX port
H
X
Z
Z
Disconnect
Table 2. PIN DESCRIPTION
2
PIN NAME
DESCRIPTION
xR, xG, xB
Analog Video I/Os
xSCL, xSCA
Analog sync I/Os
OE
Enable pin
EN
Input select
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PARAMETER DEFINITIONS
PARAMETER
DESCRIPTION
rON
Resistance between the input and output ports with the switch in the ON-state
IOZ
Output leakage current measured at the D and S ports with the switch in the OFF-state
IOS
Short circuit current measured at the I/O pins.
VIN
Voltage at the IN pin
VEN
Voltage at the EN pin
CIN
Capacitance at the control inputs (EN, IN)
COFF
Capacitance at the analog I/O port when the switch is OFF
CON
Capacitance at the analog I/O port when the switch is ON
VIH
Minimum input voltage for logic high for the control inputs (EN, IN)
VIL
Minimum input voltage for logic low for the control inputs (EN, IN)
VH
Hysteresis voltage at the control inputs (EN, IN)
VIK
I/O and control inputs diode clamp voltage (EN, IN)
VI
Voltage applied to the I/O pins when I/O is the switch input.
VO
Voltage applied to the I/O pins when I/O is the switch output.
IIH
Input high leakage current of the control inputs (EN, IN)
IIL
Input low leakage current of the control inputs (EN, IN)
II
Current into the I/O pins when I/O is the switch input.
IO
Current into the I/O pins when I/O is the switch output.
Ioff
Output leakage current measured at the I/O ports with VCC = 0
tON
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned
ON.
tOFF
Propagation delay measured between 50% of the digital input to 90% of the analog output when switch is turned
OFF.
BW
Frequency response of the switch in the ON-state measured at –3 dB
XTALK
Unwanted signal coupled from channel to channel. Measured in –dB. XTALK = 20 LOG VOUT/VIN. This is a
non-adjacent crosstalk.
OIRR
Off-isolation is the resistance (measured in –dB) between the input and output with the switch OFF.
DG
Magnitude variation between analog input and output pins when the switch is ON and the DC offset of composite
video signal varies at the analog input pin. In NTSC standard the frequency of the video signal is 3.58 MHz and
DC offset is from 0 to 0.714 V.
DP
Phase variation between analog input and output pins when the switch is ON and the DC offset of composite
video signal varies at the analog input pin. In NTSC standard the frequency of the video signal is 3.58 MHz and
DC offset is from 0 to 0.714 V.
ICC
Static power supply current
ICCD
Variation of ICC for a change in frequency in the control inputs (EN, IN)
ΔICC
This is the increase in supply current for each control input that is at the specified voltage level, rather than VCC or
GND.
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LOGIC DIAGRAM (XX GATE)
1R
AR
SW
SW
SW
2R
SW
BR
1SCL
SW
ASCL
SW
SW
2SCL
SW
BSCL
OE
SEL
4
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R
G
B
H.Sync
V.Sync
VGA
Graphics
(3.3V)
SDA
SCL
VGA Connector
Logic Control
TS5V522C
R
G
B
H.Sync
V.Sync
VGA
Graphics
(3.3V)
SDA
SCL
Docking Station
Connector
CBT3257C
Figure 1. Typical Design Examples for Dual VGA Source Signal Exchange
VCC = + 3.3V
VCC = + 5V
VCC = + 5V
SW
SW
SW
SW
Design Notes:
1. DDC (SCL,SDA) is open drain I2C Bus type and need pull up resistors.
N-Channel FET Switch allow to pull up desired Vcc Level not exceeding the
Vcc of FET Switch
2. VGA (H.Sync, V.Sync) are TTL/CMOS Type from the source of V ideo and it may
required pull up to achieve as high as 5V Signal level to meet VGA Specifications too.
Figure 2. Typical Design Example for Level Shifting with N-Channel FET Switch
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7
V
VIN
Control input voltage range (2) (3)
–0.5
7
V
VI/O
Output voltage range (2) (3) (4)
–0.5
7
IIK
Control input clamp current
VIN < 0
II/OK
I/O port clamp current
VI/O < 0
II/O
ON-state switch current (5)
Continuous current through VCC or GND
±100
mA
150
°C
Tstg
(1)
(2)
(3)
(4)
(5)
–65
Storage temperature range
V
–50
mA
–50
mA
±128
mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All input and output negative voltages are with respect to ground unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions of II/O.
THERMAL IMPEDANCE RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
θJA
(1)
Package thermal impedance
DBQ package (1)
90
PW package (1)
108
°C/W
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage
4
5.5
V
VIH
High-level control input voltage (EN, IN)
2
5.5
V
VIL
Low-level control input voltage (EN, IN)
0
0.8
V
VANALOG
Analog input/output voltage
0
VCC
V
TA
Operating free-air temperature
–40
85
V
(1)
6
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implication of slow or Floating CMOS Inputs, literature number SCBA004.
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ELECTRICAL CHARACTERISTICS (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP (2)
MIN
IIN = –18 mA
V
400
mV
VIN and VEN = VCC
±1
µA
VIN and VEN = GND
±1
µA
EN, IN
VH
EN, IN
IIH
EN, IN
VCC = 5.5 V,
IIL
EN, IN
VCC = 5.5 V,
VCC = 5.5 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF
±10
IOS
VCC = 5.5 V,
VO = 0 to 5.5 V,
VI = 0,
Switch ON
±110
Ioff
VCC = 0 V,
VO = 0 to 5.5 V,
VI = 0
ICC
VCC = 5.5 V,
II/O = 0,
Switch ON or OFF
VCC = 5.5 V,
One input at 3.4 V,
Other Inputs at VCC or
GND
2.5
VCC = 5.5 V,
VEN = GND,
I/O ports are open,
VIN switching 50% duty
cycle
0.25
IOZ
ΔICC
EN, IN
ICCD
Cin
EN, IN
VIN or VEN = 0 V,
f = 1 MHz
COFF
D port
VI/O = 3 V or 0 V,
Switch OFF,
S port
CON
rON
(1)
(2)
(3)
(4)
mA
±1
µA
3
µA
mA
mA/MHz
pF
8.5
pF
5.5
f = 1MHz, output open,
VCC = 4.5 V,
µA
3..5
VIN = VCC or GND
Switch ON,
VI = 0 V,
(4)
UNIT
–1.8
VIK
(3)
VCC = 4.5 V,
MAX
Switch ON
16.5
pF
VI = 1 V,
IO = 13 mA, RL = 75Ω
3
7
VI = 2 V,
IO = 26 mA, RL = 75Ω
3
10
Ω
VI, VO, II, and IO refer to the I.O pins.
All typical values are at VCC = 5 V (unless otherwise noted). TA = 25°C
For I/O ports, the parameter IOZ includes the input leakage current.
Measured by the voltage drop between the D and S terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (S or D) terminals.
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted), see Figure 9
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tON
S
D
1
6.6
ns
tOFF
S
D
1
6.0
ns
MAX
UNIT
MIN
TYP
MAX
UNIT
DYNAMIC CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ±10%(unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP (1)
DG
RL = 150 Ω, f = 3.58 MHz, see Figure 10
0.37
DP
RL = 150 Ω, f = 3.58 MHz, see Figure 10
0.0330
Deg
BW
RL = 150 Ω, see Figure 11
380
MHz
XTALK
RIN = 10 Ω, RL = 150 Ω, f = 10 MHz, see
Figure 11
–83
OIRR
RL = 150 Ω, f = 10 MHz, see Figure 11
–44
%
dB
dB
All typical values are at VCC = 5V (unless otherwise noted). TA = 25°C.
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over recommended operating free-air temperature range, VCC = 5 V ±10%(unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
DG
RL = 75 Ω, f = 3.58 MHz, see Figure 10
0.37
DP
RL = 75 Ω, f = 3.58 MHz, see Figure 10
0.0330
Deg
BW
RL = 75 Ω, see Figure 11
330
MHz
XTALK
RIN = 10 Ω, RL = 150Ω, f = 10 MHz, see
Figure 11
–83
OIRR
RL = 75 Ω, f = 10 MHz, see Figure 11
–44
%
dB
dB
All typical values are at VCC = 5V (unless otherwise noted). TA = 25°C.
20
0
0
Gain at -3dB, 368MHz
-1
250
10
-10
200
0
160
Phase at -3dB, -32°
-10
-20
-4
-40
-5
-20
-30
50
-40
0
-50
-50
Phase at 10 MHz, -86°
Phase - Deg
-30
Off Isolation - dB
-3
100
Phase - Deg
Gain - dB
-2
-60
-100
-50
-70
-150
-80
-6
-60
-200
-90
-7
1.00E+06
-100
1.00E+06
-70
1.00E+09
1.00E+08
1.00E+07
f- Frequency - MHz
Figure 3. Frequency Response
Crosstalk at 10 MHz, -81 dB
1.00E+07
1.00E+08
f - Frequency - MHz
-250
1.00E+09
Figure 4. Non-adjacent Crosstalk vs Frequency
20
180
10
160
0.0
-0.495
Differential Gain at 0.714V, 38%
-0.1
-0.5
-0.2
-0.505
-0.3
-0.51
-0.4
-0.52
-0.5
-0.525
-0.6
-0.53
0
Phase at 10MHz, 88°
-30
100
-40
80
-50
60
Differential Gain - %
-20
Phase - Deg
Off Isolation - dB
120
Differential Phase - Deg
140
-10
-60
Off isolation at 10MHz, -44dB
40
-70
20
-80
-90
1.00E+06
1.00E+07
1.00E+08
f - Frequency - MHz
0
1.00E+09
Figure 5. Off Isolation vs Frequency
8
Differential Phase at 0.714V, -0.52
-0.7
0
0.1 0.2
0.3 0.4 0.5 0.6 0.7
Vbias - V
0.8 0.9
-0.535
1.0
Figure 6. Differential Phase/Gain vs Vbias
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Table 3. UNDERSHOOT CHARACTERISTICS (see Figure 7 and Figure 8)
PARAMETER
VOUTU
TEST CONDITIONS
VCC = 5.5 V,
Switch OFF,
VCC
Input
Generator
11 V
Input
(Open
Socket)
100 kΩ
50 Ω
Ax
DUT
MIN
TYP
2
VOH – 0.3
VIN = VCC or GND
MAX
UNIT
V
5.5 V
90 %
90 %
2 ns
2 ns
10 %
10 %
Bx
−2 V
20 ns
100 kΩ
10 pF
VS
Output
(VOUTU)
VOH
VOH − 0.3
Figure 8. Transient Input Voltage (VI) and Output
Voltage (VOUTU) Waveforms (Switch OFF)
Figure 7. Device Test Setup
PARAMETER MEASUREMENT INFORMATION
VCC
Input Generator
VIN
IN
50 Ω
50 Ω
VG1
S1 DUT
TEST CIRCUIT
VS1
S2
D
VO
EN
VS2
CL
(see Note A)
RL
TEST
VCC
RL
CL
VS1
V S2
tON
5 V ± 0.5 V
5 V ± 0.5 V
75 Ω
75 Ω
20 pF
20 pF
GND
3V
3V
GND
tOFF
5 V ± 0.5 V
5 V ± 0.5 V
75 Ω
75 Ω
20 pF
20 pF
GND
3V
3V
GND
3V
Output
Control
(VIN)
50%
50%
0V
tON
tOFF
3V
Analog Output
Waveform
(VO)
90%
90%
0V
VOLTAGE WAVEFORMS
tON and tOFF TIMES
Figure 9. Test Circuit and Voltage Waveforms
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Ω
For additional information, refer to the TI application report, Measuring Differential Gain and Phase, literature number
SLOA040.
Figure 10. Test Circuit for Differential Gain/Phase Measurement
The differential gain and phase is measured at the output of the ON channel. For example, when VIN = 0, VEN =
0, and DA is the input, the output is measured at S1A.
HP8753ES Setup
Average = 20
RBW = 300 Hz
Smoothing = 2%
VBIAS = 0 to 1 V
ST = 1.381 s.
P1 = –7 dBM
CW frequency = 3.58 MHz
10
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Ω
Figure 11. Test Circuit for Frequency Response, Crosstalk, and OFF-Isolation
The frequency response is measured at the output of the ON channel. For example, when VIN = 0, VEN = 0, and
DA is the input, the output is measured at S1A. All unused analog I/O ports are held at VCC or GND.
The crosstalk is measured at the output of the non-adjacent ON channel. For example, when VIN = 0, VEN = 0,
and DA is the input, the output is measured at S1B. All unused analog I/O ports are held at VCC or GND.
The off-isolation is measured at the output of the OFF channel. For example, when VIN = 0, VEN = VCC, and DA is
the input, the output is measured at S1A. All unused analog I/O ports are held at VCC or GND.
HP8753ES Setup
Average = 4
RBW = 3 kHz
Smoothing = 0%
VBIAS = 0.35 V
ST = 2 s
P1 = 0 dBM
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PACKAGE OPTION ADDENDUM
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4-Apr-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TS5V522CDBQR
ACTIVE
SSOP/QSOP
DBQ
24
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TS5V522CPWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION
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1-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TS5V522CDBQR
SSOP/
QSOP
DBQ
24
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
TS5V522CPWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
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Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Apr-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TS5V522CDBQR
SSOP/QSOP
DBQ
24
2500
346.0
346.0
33.0
TS5V522CPWR
TSSOP
PW
24
2000
346.0
346.0
33.0
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Pack Materials-Page 2
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