Download STEVAL-ISA053V2

STEVAL-ISA053V2
Demonstration board for the PM6680A dual synchronous
step-down controller with adjustable output voltages plus LDO
Data Brief
Features
■
Constant on-time control allows very fast load
transients
■
6 V to 36 V input voltage range
■
5 V auxiliary output voltage
■
Adjustable switching outputs
■
Lossless current sensing
■
Negative current limit
■
Soft-start internally fixed at 2.8 ms
■
Soft-end for output discharge
■
200 kHz / 300 kHz, 300 kHz / 400 kHz, 400 kHz
/ 500 kHz (OUT1 / OUT2 selectable switching
frequency)
■
Selectable pulse skip and no-audible skip
modes at light loads
■
Independent power good signals
STEVAL-ISA053V2
Description
The PM6680A is a dual step-down controller with
adjustable output voltages. This demonstration
board is designed to test the performance of the
PM6680A by employing a typical application
circuit which allows testing of all the PM6680A
device functions. The kit features two switching
sections, with (typically) 3.3 V and 1.8 V outputs,
from a 6 V to 36 V input voltage.
The typical operating switching frequency of the
two switching sections is 200 kHz / 300 kHz,
respectively. Each switching section delivers more
than 2.5 A of output current.
Moreover, an internal linear regulator can provide
5 V @ 100 mA peak current.
June 2008
Rev 1
For further information contact your local STMicroelectronics sales office.
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OUT1-
J8
1
1
OUT5V
OUT1+
J4
2
1
R27
?
SGND
3
FB1
R28
?
C25
100n
S9
JP3SO
2
1
PGND
1K
R24
330uF
+ C11
S5
JP2SO
2
330uF
+ C12
SGND
D2
SMA
5V
C23
10pF
1
NM
NM
L2
R4
NM
C14
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V5SW
OUT5V
R17
560K
R16
100K
SGND
VIN
100pF
C16
C10
100n
R19
560K
M2
MOSFET-N-SO8
PGND
8
7
6
5
3
2
1
8
7
6
5
PGND
1
2
SGND
C18
NM
4
V+
V+
EXT5V
J11
100K
100K
PGOOD2
PGOOD1
J7
J6
V+
V+
M4
MOSFET-N-SO8
4
C6
100n
BOOT1
R13
R1
R12
R1
0R
R23
3
R8
1
R14
R15
OUT5V
V5SW
S2
SWDIP-4
100K
100K
SGND
BOOT2
LDO_FB
500R
0R
R22
10R
R10
BAT54A/SOT
5
27
26
16
30
29
17
20
15
21
22
23
SGND
SHDN
PGOOD2
PGOOD1
LDO_FB
COMP1
OUT1
V5SW
CSENSE1
LGATE1
PHASE1
HGATE1
BOOT1
220nF
C22
R9
47R
V+
BOOT2
CREF
100n
SGND
U1
7
28
6
2
8
1
14
12
13
11
10
9
SGND
+
C27
1uF
S10
JP4I
LDO_FB
SGND
FB1
2
S13
S1
2
S12
S1
2
500R
R7
SGND
0R
PGND
0R
R20
10R
R11
SGND
RLD5V
100K
R21
R2
C21
4u7
PM6681_VFQFPN32
LDO
FB1
FB2
COMP2
OUT2
SGND
PGND
CSENSE2
LGATE2
PHASE2
HGATE2
SGND
C20
1uF
EN2
4
V+
EN1
25
3
2
1
18
VREF
C4
15u
8
7
6
5
1
2
3
4
31
VCC
19
VIN
SKIP
SKI
32
LDO5
LDO
FSEL
FSE
3
24
C3
15u
2
BOOT1
4
2
3
1
R6
VIN
JP3SO
S1
JP2SO
1
JP2SO
1
3
1
+
4
4
SGND
C5
100n
C19
100n
S3
JP4I
+
V+
SGND
SGND
R26
3R9
C26
4u7
LIKE 4-PIN JUMPER
A - S12 CLOSED
B - S14 CLOSED
C - S12.1 TO S14.2
SGND
BOOT2
2
V+
3
C28
4u7
PGND
M1
MOSFET-N-SO8
5
6
7
8
1
2
3
SGND
R33
?
D3
SMA
SGND
R31
?
R32
?
1
1K
PGND
NM
+ C7
150pF
1
PGND
S4
JP2SO
R25
LDO_ADJ
C24
100n
2
PGND
NM
+ CIN
C15
C9
100n
R18
560K
3V3
NM
L1
NM
R5
NM
C13
C2
15u
R3
PGND
C17
NM
C1
15u
SGND
M3
MOSFET-N-SO8
5
6
7
8
1
2
3
D1
4
1
2
2
1
J3
LDO5V+
R29
?
R30
?
VIN
SGND
NM
+ C8
1
1
J2
-VIN
J5
+VIN
1
3
PGND
S8
JP3SO
1
1
PGND
J10
OUT2-
OUT2+
J1
J9
1
Figure 1.
2
1
1
Circuit schematic
STEVAL-ISA053V2
Circuit schematic
Schematic diagram
STEVAL-ISA053V2
2
Revision history
Revision history
Table 1.
Document revision history
Date
Revision
06-June-2008
1
Changes
Initial release.
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STEVAL-ISA053V2
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