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Super Sequencer with
Voltage Readback ADC
ADM1064
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AUX1 AUX2
REFIN
REFOUT REFGND
ADM1064
MUX
VX1
VX2
VX3
VX4
VX5
VREF
12-BIT
SAR ADC
SDA SCL A1
A0
SMBus
INTERFACE
EEPROM
PDO1
DUALFUNCTION
INPUTS
CONFIGURABLE
OUTPUT
DRIVERS
(LOGIC INPUTS
OR
SFDs)
(HV CAPABLE OF
DRIVING GATES
OF N-FET)
PDO4
CONFIGURABLE
OUTPUT
DRIVERS
PDO7
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO9
PDO2
PDO3
PDO5
PDO6
SEQUENCING
ENGINE
VP1
VP2
VP3
VP4
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
VH
AGND
PDO8
PDO10
PDOGND
VDD
ARBITRATOR
VCCP
GND
VDDCAP
04633-001
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to
14.4 V on VH
6 V on VP1 to VP4 (VPx)
5 dual-function inputs, VX1 to VX5 (VXx)
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 (PDOx)
Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external
N-FET (PDO1 to PDO6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input (REFIN) has 2 input options
Driven directly from 2.048 V (±0.25%) REFOUT pin
More accurate external reference for improved ADC
performance
Device powered by the highest of VPx, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and
48-lead, 7 mm × 7 mm TQFP packages
Figure 1.
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APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1064 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1064 integrates a 12-bit ADC that
can be used to accurately read back up to 12 separate voltages.
The device also provides up to 10 programmable inputs for monitoring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs can
provide up to a 12 V output for driving the gate of an N-FET
that can be placed in the path of a supply.
For more information about the ADM1064 register map,
refer to the AN-698 Application Note at www.analog.com.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.
ADM1064
TABLE OF CONTENTS
Features .............................................................................................. 1
Default Output Configuration.................................................. 16
Functional Block Diagram .............................................................. 1
Sequencing Engine ......................................................................... 17
Applications....................................................................................... 1
Overview ..................................................................................... 17
General Description ......................................................................... 1
Warnings...................................................................................... 17
Revision History ............................................................................... 2
SMBus Jump (Unconditional Jump)........................................ 17
Detailed Block Diagram .................................................................. 3
Sequencing Engine Application Example ............................... 18
Specifications..................................................................................... 4
Fault and Status Reporting........................................................ 19
Pin Configurations and Function Descriptions ........................... 7
Voltage Readback............................................................................ 20
Absolute Maximum Ratings............................................................ 9
Supply Supervision with the ADC ........................................... 20
Thermal Resistance ...................................................................... 9
Applications Diagram .................................................................... 21
ESD Caution.................................................................................. 9
Communicating with the ADM1064........................................... 22
Typical Performance Characteristics ........................................... 10
Configuration Download at Power-Up................................... 22
Powering the ADM1064 ................................................................ 13
Updating the Configuration ..................................................... 22
Inputs................................................................................................ 14
Updating the Sequencing Engine............................................. 23
Supply Supervision..................................................................... 14
Internal Registers........................................................................ 23
Programming the Supply Fault Detectors............................... 14
EEPROM ..................................................................................... 23
Input Comparator Hysteresis.................................................... 14
Serial Bus Interface..................................................................... 23
Input Glitch Filtering ................................................................. 15
SMBus Protocols for RAM and EEPROM.............................. 26
Supply Supervision with VXx Inputs....................................... 15
Write Operations ........................................................................ 26
VXx Pins as Digital Inputs ........................................................ 15
Read Operations......................................................................... 27
Outputs ............................................................................................ 16
Outline Dimensions ....................................................................... 29
Supply Sequencing Through Configurable Output Drivers...... 16
Ordering Guide .......................................................................... 29
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REVISION HISTORY
5/08—Rev. B to Rev. C
Changes to Table 1............................................................................ 4
Changes to Powering the ADM1064 Section ............................ 13
Changes to Table 5.......................................................................... 14
Changes to Default Output Configuration Section ................... 16
Changes to Sequence Detector Section ....................................... 18
Changes to Configuration Download at Power-Up Section..... 22
Changes to Table 10........................................................................ 23
Changes to Figure 41 and Error Correction Section ................. 28
Changes to Ordering Guide .......................................................... 29
10/06—Rev. A to Rev B
Changes to Features.......................................................................... 1
Changes to Figure 2.......................................................................... 3
Changes to Table 1............................................................................ 4
Changes to Table 2............................................................................ 7
Changes to Table 3............................................................................ 9
Added Table 4.................................................................................... 9
Changes to Inputs Section............................................................. 14
Changes to Outputs Section.......................................................... 17
Added Default Output Configuration Section ........................... 18
Changes to Fault Reporting Section ............................................ 22
Changes to Voltage Readback Section......................................... 23
Changes to Identifying the ADM1064 on the SMBus Section. 27
Changes to Figure 31 and Figure 32............................................. 28
Changes to Figure 43 Caption ...................................................... 32
Change to Ordering Guide............................................................ 32
1/05—Rev. 0 to Rev A
Changes to Figure 1...........................................................................1
Changes to Absolute Maximum Ratings Section..........................8
Change to Supply Sequencing through Configurable
Output Drivers Section.................................................................. 16
Changes to Figure 33...................................................................... 21
Change to Table 9 ........................................................................... 24
10/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
ADM1064
The logical core of the device is a sequencing engine (SE). This
state machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs, based
on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.
DETAILED BLOCK DIAGRAM
REFIN
REFOUT
AUX2 AUX1
REFGND SDA SCL A1
ADM1064
SMBus
INTERFACE
VREF
12-BIT
SAR ADC
DEVICE
CONTROLLER
GPI SIGNAL
CONDITIONING
VX1
A0
OSC
EEPROM
CONFIGURABLE
OUTPUT DRIVER
(HV)
SFD
PDO1
PDO2
VX2
PDO3
VX3
PDO4
PDO5
GPI SIGNAL
CONDITIONING
VX5
SFD
SEQUENCING
ENGINE
CONFIGURABLE
OUTPUT DRIVER
(HV)
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VP1
SELECTABLE
ATTENUATOR
SFD
VP2
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO6
PDO7
VP3
PDO8
VP4
PDO9
VH
SELECTABLE
ATTENUATOR
SFD
AGND
VDDCAP
REG 5.25V
CHARGE PUMP
VDD
ARBITRATOR
GND
VCCP
Figure 2. Detailed Block Diagram
Rev. C | Page 3 of 32
CONFIGURABLE
OUTPUT DRIVER
(LV)
PDO10
PDOGND
04633-002
VX4
ADM1064
SPECIFICATIONS
VH = 3.0 V to 14.4 V 1 , VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY ARBITRATION
VH, VPx
VPx
VH
VDDCAP
CVDDCAP
POWER SUPPLY
Supply Current, IVH, IVPx
Additional Currents
All PDO FET Drivers On
Min
Typ
Max
Unit
Test Conditions/Comments
4.75
6.0
14.4
5.4
V
V
V
V
μF
Minimum supply required on one of VH, VPx pins
Maximum VDDCAP = 5.1 V, typical
VDDCAP = 4.75 V
Regulated LDO output
Minimum recommended decoupling capacitance
4.2
6
mA
VDDCAP = 4.75 V, PDO1 to PDO10 off, ADC off
mA
3.0
2.7
10
1
1
10
mA
mA
VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA
each, PDO7 to PDO10 off
Maximum additional load that can be drawn from all
PDO pull-ups to VDDCAP
Running round-robin loop
1 ms duration only, VDDCAP = 3 V
52
±0.05
kΩ
%
Midrange and high range
Current Available from VDDCAP
ADC Supply Current
EEPROM Erase Current
SUPPLY FAULT DETECTORS
VH Pin
Input Impedance
Input Attenuator Error
Detection Ranges
High Range
Midrange
VPx Pins
Input Impedance
Input Attenuator Error
Detection Ranges
Midrange
Low Range
Ultralow Range
VXx Pins
Input Impedance
Detection Ranges
Ultralow Range
Absolute Accuracy
2
mA
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6
2.5
52
±0.05
2.5
1.25
0.573
Input Reference Voltage on REFIN Pin, VREFIN
Resolution
INL
Gain Error
6
3
1.375
1
V
V
kΩ
%
Low range and midrange
V
V
V
No input attenuation error
MΩ
0.573
Threshold Resolution
Digital Glitch Filter
ANALOG-TO-DIGITAL CONVERTER
Signal Range
14.4
6
1.375
±1
8
0
100
V
%
Bits
μs
μs
0
VREFIN
V
±2.5
±0.05
V
Bits
LSB
%
2.048
12
Rev. C | Page 4 of 32
No input attenuation error
VREF error + DAC nonlinearity + comparator offset error
+ input attenuation error
Minimum programmable filter length
Maximum programmable filter length
The ADC can convert signals presented to the VH,
VPx, and VXx pins; VPx and VH input signals are
attenuated depending on the selected range; a signal
at the pin corresponding to the selected range is
from 0.573 V to 1.375 V at the ADC input.
Endpoint corrected, VREFIN = 2.048 V
VREFIN = 2.048 V
ADM1064
Parameter
Conversion Time
Min
Offset Error
Input Noise
REFERENCE OUTPUT
Reference Output Voltage
Load Regulation
Minimum Load Capacitance
PSRR
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1 to PDO6)
Output Impedance
VOH
IOUTAVG
Standard (Digital Output) Mode
(PDO1 to PDO10)
VOH
Typ
0.44
84
Max
±2
0.25
2.043
2.048
−0.25
0.25
2.053
1
60
11
10.5
500
12.5
12
20
14
13.5
2.4
VPU − 0.3
0
Test Conditions/Comments
One conversion on one channel
All 12 channels selected, averaging enabled
VREFIN = 2.048 V
Direct input (no attenuator)
V
mV
mV
μF
dB
No load
Sourcing current
Sinking current
Capacitor required for decoupling, stability
DC
kΩ
V
V
μA
IOH = 0 μA
IOH = 1 μA
2 V < VOH < 7 V
0.50
20
60
29
2
V
V
V
V
mA
mA
kΩ
mA
10
110
μA
kHz
4.5
VOL
IOL 2
ISINK2
RPULL-UP
ISOURCE (VPx)2
Unit
ms
ms
LSB
LSB rms
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
VPU to VPx = 6.0 V, IOH = 0 mA
VPU ≤ 2.7 V, IOH = 0.5 mA
IOL = 20 mA
Maximum sink current per PDOx pin
Maximum total sink for all PDOx pins
Internal pull-up
Current load on any VPx pull-ups, that is, total source
current available through any number of PDOx pull-up
switches configured onto any one VPx pin
VPDO = 14.4 V
All on-chip time delays derived from this clock
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Three-State Output Leakage Current
Oscillator Frequency
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
Input Low Voltage, VIL
Input High Current, IIH
Input Low Current, IIL
Input Capacitance
Programmable Pull-Down Current, IPULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
Input Low Voltage, VIL
Output Low Voltage, VOL2
SERIAL BUS TIMING
Clock Frequency, fSCLK
Bus Free Time, tBUF
Start Setup Time, tSU;STA
Stop Setup Time, tSU;STO
Start Hold Time, tHD;STA
SCL Low Time, tLOW
SCL High Time, tHIGH
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
16
20
90
100
2.0
0.8
−1
1
5
20
2.0
0.8
0.4
400
4.7
4.7
4
4
4.7
4
1000
300
V
V
μA
μA
pF
μA
V
V
V
kHz
μs
μs
μs
μs
μs
μs
μs
μs
Rev. C | Page 5 of 32
Maximum VIN = 5.5 V
Maximum VIN = 5.5 V
VIN = 5.5 V
VIN = 0
VDDCAP = 4.75 V, TA = 25°C, if known logic state is
required
IOUT = −3.0 mA
ADM1064
Parameter
Data Setup Time, tSU;DAT
Data Hold Time, tHD;DAT
Input Low Current, IIL
SEQUENCING ENGINE TIMING
State Change Time
1
2
Min
250
5
Typ
Max
1
10
Unit
ns
ns
μA
Test Conditions/Comments
VIN = 0 V
μs
At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.
Specification is not production tested but is supported by characterization data at initial product release.
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Rev. C | Page 6 of 32
ADM1064
PDOGND
NC
31
VCCP
PDOGND
32
A0
VCCP
33
A1
A0
34
SCL
A1
35
SDA
SCL
36
AUX2
SDA
37
AUX1
AUX2
38
VDDCAP
AUX1
39
GND
VDDCAP
40
NC
GND
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
NC 1
VX1 1
30 PDO1
36 NC
PIN 1
INDICATOR
VX1 2
35 PDO1
VX2 3
34 PDO2
29 PDO2
VX3 4
33 PDO3
VX3 3
28 PDO3
VX4 5
VX4 4
27 PDO4
VX5 6
ADM1064
26 PDO5
VP1 7
25 PDO6
VP2 8
TOP VIEW
(Not to Scale)
VP2 7
24 PDO7
VP3 9
28 PDO8
VP3 8
23 PDO8
VP4 10
27 PDO9
VP4 9
22 PDO9
VH 11
26 PDO10
21 PDO10
NC 12
25 NC
REFOUT
NC
NC
NC
NC
NC
NC
NC = NO CONNECT
13
14
15
16
17
18
19
20
21
22
23
24
NC = NO CONNECT
Figure 3. LFCSP Pin Configuration
04633-004
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
14
29 PDO7
NC
13
04633-003
12
REFIN
AGND
11
REFGND
VH 10
30 PDO6
REFOUT
VP1 6
31 PDO5
REFIN
TOP VIEW
(Not to Scale)
REFGND
ADM1064
VX5 5
32 PDO4
NC
VX2 2
AGND
PIN 1
INDICATOR
Figure 4. TQFP Pin Configuration
Table 2. Pin Function Descriptions
Pin No.
LFCSP 1 TQFP
15 to
1, 12, 13,
20
18 to 25,
36, 37, 48
1 to 5
2 to 6
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Mnemonic
NC
Description
No Connection.
VX1 to VX5
(VXx)
VP1 to VP4
(VPx)
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to
1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a
supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and
from 0.573 V to 1.375 V.
High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.
The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be
connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
Programmable Output Drivers.
6 to 9
7 to 10
10
11
VH
11
12
13
14
15
16
AGND 2
REFGND
REFIN
14
17
REFOUT2
21 to
30
31
32
26 to 35
38
39
PDO10 to
PDO1
PDOGND2
VCCP
33
34
35
36
37
38
40
41
42
43
44
45
A0
A1
SCL
SDA
AUX2
AUX1
Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND. A 10 μF capacitor is recommended for this purpose.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
Auxiliary, Single-Ended ADC Input.
Auxiliary, Single-Ended ADC Input.
Rev. C | Page 7 of 32
ADM1064
Pin No.
LFCSP 1 TQFP
39
46
Mnemonic
VDDCAP
40
GND2
1
2
47
Description
Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is
recommended for this purpose.
Supply Ground.
Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.
In a typical application, all ground pins are connected together.
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Rev. C | Page 8 of 32
ADM1064
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Voltage on VH Pin
Voltage on VPx Pins
Voltage on VXx Pins
Voltage on A0, A1 Pins
Voltage on REFIN, REFOUT Pins
Voltage on VDDCAP, VCCP Pins
Voltage on PDOx Pins
Voltage on SDA, SCL Pins
Voltage on AUX1, AUX2 Pins
Voltage on GND, AGND, PDOGND, REFGND Pins
Input Current at Any Pin
Package Input Current
Maximum Junction Temperature (TJ max)
Storage Temperature Range
Lead Temperature,
Soldering Vapor Phase, 60 sec
Rating
16 V
7V
−0.3 V to +6.5 V
−0.3 V to +7 V
5V
6.5 V
16 V
7V
−0.3 V to +5 V
−0.3 V to +0.3 V
±5 mA
±20 mA
150°C
−65°C to +150°C
215°C
ESD Rating, All Pins
2000 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
40-Lead LFCSP
48-Lead TQFP
ESD CAUTION
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Rev. C | Page 9 of 32
θJA
25
50
Unit
°C/W
°C/W
ADM1064
TYPICAL PERFORMANCE CHARACTERISTICS
180
6
160
5
140
120
IVP1 (µA)
VVDDCAP (V)
4
3
100
80
60
2
40
1
0
1
2
3
4
5
0
6
04633-053
04633-050
0
20
0
1
2
3
VVP1 (V)
4
5
6
VVP1 (V)
Figure 5. VVDDCAP vs. VVP1
Figure 8. IVP1 vs. VVP1 (VP1 Not as Supply)
6
5.0
4.5
5
4.0
3.5
3.0
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IVH (mA)
3
2
2.0
1.5
1.0
04633-051
1
0
2.5
0
2
4
6
8
10
12
14
04633-054
VVDDCAP (V)
4
0.5
0
16
0
2
4
6
VVH (V)
8
10
12
14
16
VVH (V)
Figure 6. VVDDCAP vs. VVH
Figure 9. IVH vs. VVH (VH as Supply)
350
5.0
4.5
300
4.0
250
IVH (µA)
3.0
2.5
2.0
1.5
200
150
100
1.0
0
1
2
3
4
5
0
6
VVP1 (V)
04633-055
0.5
0
50
04633-052
IVP1 (mA)
3.5
0
1
2
3
4
VVH (V)
Figure 7. IVP1 vs. VVP1 (VP1 as Supply)
Figure 10. IVH vs. VVH (VH Not as Supply)
Rev. C | Page 10 of 32
5
6
ADM1064
14
1.0
0.8
0.6
10
0.4
8
0.2
DNL (LSB)
6
0
–0.2
–0.4
4
–0.6
0
04633-056
2
0
2.5
5.0
7.5
10.0
12.5
04633-066
CHARGE-PUMPED V PDO1 (V)
12
–0.8
–1.0
15.0
0
1000
5.0
1.0
4.5
0.8
4.0
0.6
3.5
0.4
3.0
VP1 = 5V
2.5
VP1 = 3V
4000
0.2
0
–0.2
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1.5
–0.4
1.0
0
1
2
3
4
5
04633-063
04633-057
–0.6
0.5
0
3000
Figure 14. DNL for ADC
INL (LSB)
VPDO1 (V)
Figure 11. Charge-Pumped VPDO1 (FET Drive Mode) vs. ILOAD
2.0
2000
CODE
ILOAD (µA)
–0.8
–1.0
6
0
1000
2000
3000
4000
CODE
ILOAD (mA)
Figure 12. VPDO1 (Strong Pull-Up to VPx) vs. ILOAD
Figure 15. INL for ADC
4.5
12000
4.0
9894
10000
3.5
2.5
VP1 = 3V
2.0
1.5
8000
6000
4000
1.0
0
0
10
20
30
40
50
25
0
60
2047
81
2048
2049
CODE
ILOAD (µA)
Figure 16. ADC Noise, Midcode Input, 10,000 Reads
Figure 13. VPDO1 (Weak Pull-Up to VPx) vs. ILOAD
Rev. C | Page 11 of 32
04633-064
2000
0.5
04633-058
VPDO1 (V)
HITS PER CODE
VP1 = 5V
3.0
ADM1064
2.058
VP1 = 3.0V
2.048
VP1 = 4.75V
2.043
2.038
–40
04633-061
REFOUT (V)
2.053
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. REFOUT vs. Temperature
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Rev. C | Page 12 of 32
ADM1064
POWERING THE ADM1064
An external capacitor to GND is required to decouple the on-chip
supply from noise. This capacitor should be connected to the
VDDCAP pin, as shown in Figure 18. The capacitor has another
use during brownouts (momentary loss of power). Under these
conditions, when the input supply (VPx or VH) dips transiently
below VDD, the synchronous rectifier switch immediately turns
off so that it does not pull VDD down. The VDD capacitor can
then act as a reservoir to keep the device active until the next
highest supply takes over the powering of the device. A 10 μF
capacitor is recommended for this reservoir/decoupling function.
When two or more supplies are within 100 mV of each other,
the supply that first takes control of VDD keeps control. For
example, if VP1 is connected to a 3.3 V supply, VDD powers up
to approximately 3.1 V through VP1. If VP2 is then connected
to another 3.3 V supply, VP1 still powers the device, unless VP2
goes 100 mV higher than VP1.
VDDCAP
VP1
IN
OUT
4.75V
LDO
EN
VP2
IN
OUT
4.75V
LDO
EN
VP3
IN
OUT
4.75V
LDO
EN
VP4
IN
OUT
4.75V
LDO
EN
VH
IN
Rev. C | Page 13 of 32
INTERNAL
DEVICE
SUPPLY
EN
SUPPLY
COMPARATOR
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The VH input pin can accommodate supplies up to 14.4 V, which
allows the ADM1064 to be powered using a 12 V backplane
supply. In cases where this 12 V supply is hot swapped, it is
recommended that the ADM1064 not be connected directly to
the supply. Suitable precautions, such as the use of a hot swap
controller, should be taken to protect the device from transients
that could cause damage during hot swap events.
OUT
4.75V
LDO
Figure 18. VDD Arbitrator Operation
04633-022
The ADM1064 is powered from the highest voltage input on either
the positive-only supply inputs (VPx) or the high voltage supply
input (VH). This technique offers improved redundancy because
the device is not dependent on any particular voltage rail to keep
it operational. The same pins are used for supply fault detection
(see the Supply Supervision section). A VDD arbitrator on the
device chooses which supply to use. The arbitrator can be
considered an OR’ing of five low dropout regulators (LDOs)
together. A supply comparator chooses the highest input to provide
the on-chip supply. There is minimal switching loss with this
architecture (~0.2 V), resulting in the ability to power the
ADM1064 from a supply as low as 3.0 V. Note that the supply on
the VXx pins cannot be used to power the device.
ADM1064
INPUTS
SUPPLY SUPERVISION
The threshold value required is given by
The ADM1064 has 10 programmable inputs. Five of these are
dedicated supply fault detectors (SFDs). These dedicated inputs
are called VH and VPx (VP1 to VP4) by default. The other five
inputs are labeled VXx (VX1 to VX5) and have dual functionality.
They can be used either as SFDs with functionality similar to
VH and VPx, or as CMOS-/TTL-compatible logic inputs to the
device. Therefore, the ADM1064 can have up to 10 analog inputs,
a minimum of five analog inputs and five digital inputs, or
a combination thereof. If an input is used as an analog input,
it cannot be used as a digital input. Therefore, a configuration
requiring 10 analog inputs has no available digital inputs. Table 6
shows the details of each input.
VT = (VR × N)/255 + VB
where:
VT is the desired threshold voltage (undervoltage or overvoltage).
VR is the voltage range.
N is the decimal value of the 8-bit code.
VB is the bottom of the range.
Reversing the equation, the code for a desired threshold is
given by
N = 255 × (VT − VB)/VR
PROGRAMMING THE SUPPLY FAULT DETECTORS
The ADM1064 can have up to 10 SFDs on its 10 input channels.
These highly programmable reset generators enable the supervision
of up to 10 supply voltages. The supplies can be as low as 0.573 V
and as high as 14.4 V. The inputs can be configured to detect
an undervoltage fault (the input voltage drops below a preprogrammed value), an overvoltage fault (the input voltage rises above
a preprogrammed value), or an out-of-window fault (the input
voltage is outside a preprogrammed range). The thresholds can be
programmed to an 8-bit resolution in registers provided in the
ADM1064. This translates to a voltage resolution that is dependent
on the range selected.
For example, if the user wants to set a 5 V overvoltage threshold
on VP1, the code to be programmed in the PS1OVTH register
(as discussed in the AN-698 Application Note at www.analog.com)
is given by
N = 255 × (5 − 2.5)/3.5
Therefore, N = 182 (1011 0110 or 0xB6).
INPUT COMPARATOR HYSTERESIS
The UV and OV comparators shown in Figure 19 are always
monitoring VPx. To avoid chatter (multiple transitions when the
input is very close to the set threshold level), these comparators
have digitally programmable hysteresis. The hysteresis can be
programmed up to the values shown in Table 6.
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RANGE
SELECT
The resolution is given by
ULTRA
LOW
Step Size = Threshold Range/255
VREF
Therefore, if the high range is selected on VH, the step size can
be calculated as follows:
OV
COMPARATOR
–
GLITCH
FILTER
FAULT
OUTPUT
+
LOW
(14.4 V − 6.0 V)/255 = 32.9 mV
MID
–
UV
FAULT TYPE
COMPARATOR
SELECT
04633-023
Table 5 lists the upper and lower limits of each available range,
the bottom of each range (VB), and the range itself (VR).
Figure 19. Supply Fault Detector Block
Table 5. Voltage Range Limits
Voltage Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
+
VPx
VB (V)
0.573
1.25
2.5
6.0
VR (V)
0.802
1.75
3.5
8.4
The hysteresis is added after a supply voltage goes out of tolerance.
Therefore, the user can program the amount above the undervoltage threshold to which the input must rise before an
undervoltage fault is deasserted. Similarly, the user can program
the amount below the overvoltage threshold to which an input
must fall before an overvoltage fault is deasserted.
Table 6. Input Functions, Thresholds, and Ranges
Input
VH
Function
High Voltage Analog Input
VPx
Positive Analog Input
VXx
High-Z Analog Input
Digital Input
Voltage Range (V)
2.5 to 6.0
6.0 to 14.4
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
0.573 to 1.375
0 to 5.0
Maximum Hysteresis
425 mV
1.02 V
97.5 mV
212 mV
425 mV
97.5 mV
N/A
Rev. C | Page 14 of 32
Voltage Resolution (mV)
13.7
32.9
3.14
6.8
13.7
3.14
N/A
Glitch Filter (μs)
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
0 to 100
ADM1064
The hysteresis value is given by
VHYST = VR × NTHRESH/255
where:
VHYST is the desired hysteresis voltage.
NTHRESH is the decimal value of the 5-bit hysteresis code.
Note that NTHRESH has a maximum value of 31. The maximum
hysteresis for the ranges is listed in Table 6.
INPUT GLITCH FILTERING
The final stage of the SFDs is a glitch filter. This block provides
time-domain filtering on the output of the SFD comparators,
which allows the user to remove any spurious transitions such
as supply bounce at turn-on. The glitch filter function is in addition
to the digitally programmable hysteresis of the SFD comparators. The glitch filter timeout is programmable up to 100 μs.
For example, when the glitch filter timeout is 100 μs, any pulse
appearing on the input of the glitch filter block that is less than
100 μs in duration is prevented from appearing on the output of
the glitch filter block. Any input pulse that is longer than 100 μs
appears on the output of the glitch filter block. The output is
delayed with respect to the input by 100 μs. The filtering
process is shown in Figure 20.
INPUT PULSE SHORTER
THAN GLITCH FILTER TIMEOUT
INPUT PULSE LONGER
THAN GLITCH FILTER TIMEOUT
PROGRAMMED
TIMEOUT
INPUT
t0
tGF
As discussed in the Supply Supervision with VXx Inputs section,
the VXx input pins on the ADM1064 have dual functionality.
The second function is as digital logic inputs to the device.
Therefore, the ADM1064 can be configured for up to five digital
inputs. These inputs are TTL-/CMOS-compatible. Standard logic
signals can be applied to the pins: RESET from reset generators,
PWRGD signals, fault flags, manual resets, and so on. These
signals are available as inputs to the SE and, therefore, can be
used to control the status of the PDOs. The inputs can be
configured to detect either a change in level or an edge.
OUTPUT
When configured for level detection, the output of the digital
block is a buffered version of the input. When configured for
edge detection, a pulse of programmable width is output from
the digital block once the logic transition is detected. The width
is programmable from 0 μs to 100 μs.
OUTPUT
t0
tGF
04633-024
tGF
tGF
VXx PINS AS DIGITAL INPUTS
Figure 20. Input Glitch Filter Function
SUPPLY SUPERVISION WITH VXx INPUTS
The VXx inputs have two functions. They can be used as either
supply fault detectors or digital logic inputs. When selected as
analog (SFD) inputs, the VXx pins have functionality that is very
similar to the VH and VPx pins. The primary difference is that
the VXx pins have only one input range: 0.573 V to 1.375 V.
Therefore, these inputs can directly supervise only the very low
supplies. However, the input impedance of the VXx pins is high,
allowing an external resistor divide network to be connected to the
pin. Thus, potentially any supply can be divided down into the
input range of the VXx pin and supervised, enabling the ADM1064
to monitor other supplies, such as +24 V, +48 V, and −5 V.
The digital blocks feature the same glitch filter function that is
available on the SFDs. This enables the user to ignore spurious
transitions on the inputs. For example, the filter can be used to
debounce a manual reset switch.
When configured as digital inputs, each VXx pin has a weak
(10 μA) pull-down current source available for placing the input
into a known condition, even if left floating. The current source,
if selected, weakly pulls the input to GND.
VXx
(DIGITAL INPUT)
Rev. C | Page 15 of 32
+
DETECTOR
GLITCH
FILTER
TO
SEQUENCING
ENGINE
–
VREF = 1.4V
Figure 21. VXx Digital Input Function
04633-027
INPUT
t0
The secondary SFDs are fixed to the same input range as the
primary SFDs. They are used to indicate warning levels rather
than failure levels. This allows faults and warnings to be generated on a single supply using only one pin. For example, if VP1
is set to output a fault when a 3.3 V supply drops to 3.0 V, VX1
can be set to output a warning at 3.1 V. Warning outputs are
available for readback from the status registers. They are also
OR’ed together and fed into the SE, allowing warnings to generate
interrupts on the programmable driver outputs (PDOs). Therefore,
in this example, if the supply drops to 3.1 V, a warning is generated,
and remedial action can be taken before the supply drops out of
tolerance.
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PROGRAMMED
TIMEOUT
t0
An additional supply supervision function is available when the
VXx pins are selected as digital inputs. In this case, the analog
function is available as a second detector on each of the dedicated analog inputs, VPx and VH. The analog function of VX1
is mapped to VP1, VX2 is mapped to VP2, and so on. VX5 is
mapped to VH. In this case, these SFDs can be viewed as secondary
or warning SFDs.
ADM1064
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
be enabled in the PDOxCFG configuration register (see the
AN-698 Application Note at www.analog.com for details).
Supply sequencing is achieved with the ADM1064 using the
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The data sources are as follows:
•
•
The sequence in which the PDOs are asserted (and, therefore, the
supplies are turned on) is controlled by the sequencing engine (SE).
The SE determines what action is taken with the PDOs, based
on the condition of theADM1064 inputs. Therefore, the PDOs
can be set up to assert when the SFDs are in tolerance, the correct
input signals are received on the VXx digital pins, no warnings
are received from any of the inputs of the device, and at other
times. The PDOs can be used for a variety of functions. The
primary function is to provide enable signals for LDOs or dcto-dc converters that generate supplies locally on a board. The
PDOs can also be used to provide a PWRGD signal when all the
SFDs are in tolerance or a RESET output if one of the SFDs goes
out of specification (this can be used as a status signal for a DSP,
FPGA, or other microcontroller).
•
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1064 device
from the factory are set to 0. Because of this, the PDOx pins are
pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
As the input supply to the ADM1064 ramps up on VPx or VH,
all PDOx pins behave as follows:
•
•
The PDOs can be programmed to pull up to a number of different
options. The outputs can be programmed as follows:
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Open drain (allowing the user to connect an external pullup resistor).
Open drain with weak pull-up to VDD.
Open drain with strong pull-up to VDD.
Open drain with weak pull-up to VPx.
Open drain with strong pull-up to VPx.
Strong pull-down to GND.
Internally charge-pumped high drive (12 V, PDO1 to
PDO6 only).
The internal pull-down can be overdriven with an external pullup of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor
value is given by
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a cardside voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly. The data driving each of
the PDOs can come from one of three sources. The source can
3.3 V = 5 V × 20 kΩ/(RUP + 20 kΩ)
Therefore,
RUP = (100 kΩ − 66 kΩ)/3.3 V = 10 kΩ
VFET (PDO1 TO PDO6 ONLY)
VDD
VP4
10Ω
10Ω
20kΩ
VP1
SEL
20kΩ
CFG4 CFG5 CFG6
10Ω
SE DATA
PDO
SMBus DATA
20kΩ
CLK DATA
Figure 22. Programmable Driver Output
Rev. C | Page 16 of 32
04633-028
•
•
•
•
•
•
•
Input supply = 0 V to 1.2 V. The PDOs are high impedance.
Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND
by a weak (20 kΩ) on-chip pull-down resistor.
Supply > 2.7 V. Factory-programmed devices continue to
pull all PDOs to GND by a weak (20 kΩ) on-chip pull-down
resistor. Programmed devices download current EEPROM
configuration data, and the programmed setup is latched. The
PDO then goes to the state demanded by the configuration.
This provides a known condition for the PDOs during
power-up.
20kΩ
•
Output from the SE.
Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
On-chip clock. A 100 kHz clock is generated on the device.
This clock can be made available on any of the PDOs. It can be
used, for example, to clock an external device such as an LED.
ADM1064
SEQUENCING ENGINE
OVERVIEW
The SE state machine comprises 63 state cells. Each state has the
following attributes:
•
•
•
•
•
•
Monitors signals indicating the status of the 10 input pins,
VP1 to VP4, VH, and VX1 to VX5.
Can be entered from any other state.
Three exit routes move the state machine onto a next state:
sequence detection, fault monitoring, and timeout.
Delay timers for the sequence and timeout blocks can be
programmed independently and changed with each state
change. The range of timeouts is from 0 ms to 400 ms.
Output condition of the 10 PDO pins is defined and fixed
within a state.
Transition from one state to the next is made in less than
20 μs, which is the time needed to download a state
definition from EEPROM to the SE.
MONITOR
FAULT
STATE
TIMEOUT
SEQUENCE
04633-029
The ADM1064 sequencing engine (SE) provides the user with
powerful and flexible control of sequencing. The SE implements
a state machine control of the PDO outputs, with state changes
conditional on input events. SE programs can enable complex
control of boards, including power-up and power-down sequence
control, fault event handling, and interrupt generation on warnings.
A watchdog function that verifies the continued operation of a
processor clock can be integrated into the SE program. The SE
can also be controlled via the SMBus, giving software or firmware
control of the board sequencing.
Figure 23. State Cell
The ADM1064 offers up to 63 state definitions. The signals
monitored to indicate the status of the input pins are the
outputs of the SFDs.
WARNINGS
The SE also monitors warnings. These warnings can be generated
when the ADC readings violate their limit register value or
when the secondary voltage monitors on VPx and VH are
triggered. The warnings are OR’ed together and are available
as a single warning input to each of the three blocks that enable
exiting a state.
SMBus JUMP (UNCONDITIONAL JUMP)
The SE can be forced to advance to the next state unconditionally. This enables the user to force the SE to advance. Examples
of the use of this feature include moving to a margining state or
debugging a sequence. The SMBus jump or go-to command can
be seen as another input to sequence and timeout blocks to
provide an exit from each state.
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Table 7. Sample Sequence State Entries
State
IDLE1
IDLE2
EN3V3
Sequence
If VX1 is low , go to State IDLE2.
If VP1 is okay, go to State EN3V3.
If VP2 is okay, go to State EN2V5.
DIS3V3
EN2V5
If VX1 is high, go to State IDLE1.
If VP3 is okay, go to State PWRGD.
DIS2V5
FSEL1
FSEL2
PWRGD
If VX1 is high, go to State IDLE1.
If VP3 is not okay, go to State DIS2V5.
If VP2 is not okay, go to State DIS3V3.
If VX1 is high, go to State DIS2V5.
Timeout
Monitor
If VP2 is not okay after 10 ms,
go to State DIS3V3.
If VP1 is not okay, go to State IDLE1.
If VP3 is not okay after 20 ms,
go to State DIS2V5.
If VP1 or VP2 is not okay, go to State FSEL2.
If VP1 or VP2 is not okay, go to State FSEL2.
If VP1 is not okay, go to State IDLE1.
If VP1, VP2, or VP3 is not okay, go to State FSEL1.
Rev. C | Page 17 of 32
ADM1064
SEQUENCING ENGINE APPLICATION EXAMPLE
The application in this section demonstrates the operation of
the SE. Figure 25 shows how the simple building block of a single
SE state can be used to build a power-up sequence for a threesupply system. Table 8 lists the PDOs for each state in the same SE
implementation. In this system, a good 5 V supply on VP1 and
the VX1 pin held low are the triggers required to start a power-up
sequence. The sequence next turns on the 3.3 V supply, then the
2.5 V supply (assuming successful turn-on of the 3.3 V supply).
When all three supplies have turned on correctly, the PWRGD
state is entered, where the SE remains until a fault occurs on one
of the three supplies or until it is instructed to go through a powerdown sequence by VX1 going high.
If a timer delay is specified, the input to the sequence detector
must remain in the defined state for the duration of the timer
delay. If the input changes state during the delay, the timer is reset.
The sequence detector can also help to identify monitoring faults.
In the sample application shown in Figure 25, the FSEL1 and
FSEL2 states first identify which of the VP1,VP2, or VP3 pins
has faulted, and then they take appropriate action.
SEQUENCE
STATES
IDLE1
VX1 = 0
Faults are dealt with throughout the power-up sequence on
a case-by-case basis. The following three sections (the Sequence
Detector section, the Monitoring Fault Detector section, and
the Timeout Detector section) describe the individual blocks
and use the sample application shown in Figure 25 to demonstrate
the actions of the state machine.
IDLE2
VP1 = 1
MONITOR FAULT
STATES
EN3V3
10ms
VP1 = 0
Sequence Detector
The sequence detector block is used to detect when a step in
a sequence is complete. It looks for one of the SE inputs to
change state and is most often used as the gate for successful
progress through a power-up or power-down sequence. A timer
block that is included in this detector can insert delays into a
power-up or power-down sequence, if required. Timer delays
can be set from 10 μs to 400 ms. Figure 24 is a block diagram of
the sequence detector.
VP2 = 1
EN2V5
DIS3V3
20ms
(VP1 + VP2) = 0
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VP1
VX5
SUPPLY FAULT
DETECTION
TIMEOUT
STATES
VX1 = 1
VP3 = 1
PWRGD
DIS2V5
VP2 = 0
(VP1 + VP2 + VP3) = 0
VX1 = 1
(VP1 +
VP2) = 0
SEQUENCE
DETECTOR
FSEL1
VX1 = 1
VP3 = 0
FSEL2
LOGIC INPUT CHANGE
OR FAULT DETECTION
VP1 = 0
TIMER
VP2 = 0
04633-030
WARNINGS
INVERT
FORCE FLOW
(UNCONDITIONAL JUMP)
04633-032
Figure 25. Sample Application Flow Diagram
SELECT
Figure 24. Sequence Detector Block Diagram
Table 8. PDO Outputs for Each State
PDO Outputs
PDO1 = 3V3ON
PDO2 = 2V5ON
PDO3 = FAULT
IDLE1
0
0
0
IDLE2
0
0
0
EN3V3
1
0
0
EN2V5
1
1
0
DIS3V3
0
1
1
Rev. C | Page 18 of 32
DIS2V5
1
0
1
PWRGD
1
1
0
FSEL1
1
1
1
FSEL2
1
1
1
ADM1064
Monitoring Fault Detector
Timeout Detector
The monitoring fault detector block is used to detect a failure
on an input. The logical function implementing this is a wide
OR gate that can detect when an input deviates from its expected
condition. The clearest demonstration of the use of this block
is in the PWRGD state, where the monitor block indicates that
a failure on one or more of the VP1,VP2, or VP3 inputs has
occurred.
The timeout detector allows the user to trap a failure to ensure
proper progress through a power-up or power-down sequence.
No programmable delay is available in this block because the
triggering of a fault condition is likely to be caused by a supply
falling out of tolerance. In this situation, the device needs to
react as quickly as possible. Some latency occurs when moving
out of this state because it takes a finite amount of time (~20 μs)
for the state configuration to download from EEPROM into the SE.
Figure 26 is a block diagram of the monitoring fault detector.
MONITORING FAULT
DETECTOR
1-BIT FAULT
DETECTOR
VP1
FAULT
SUPPLY FAULT
DETECTION
The ADM1064 has a fault latch for recording faults. Two registers,
FSTAT1 and FSTAT2, are set aside for this purpose. A single bit
is assigned to each input of the device, and a fault on that input
sets the relevant bit. The contents of the fault register can be
read out over the SMBus to determine which input(s) faulted.
The fault register can be enabled/disabled in each state. To latch
data from one state, ensure that the fault latch is disabled in the
following state. This ensures that only real faults are captured
and not, for example, undervoltage conditions that may be
present during a power-up or power-down sequence.
1-BIT FAULT
DETECTOR
LOGIC INPUT CHANGE
OR FAULT DETECTION
The power-up sequence progresses when this change is
detected. If, however, the supply fails (perhaps due to a short
circuit overloading this supply), the timeout block traps the
problem. In this example, if the 3.3 V supply fails within 10 ms,
the SE moves to the DIS3V3 state and turns off this supply by
bringing PDO1 low. It also indicates that a fault has occurred by
taking PDO3 high. Timeout delays of 100 μs to 400 ms can be
programmed.
FAULT AND STATUS REPORTING
MASK
SENSE
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FAULT
MASK
SENSE
1-BIT FAULT
DETECTOR
FAULT
WARNINGS
MASK
Figure 26. Monitoring Fault Detector Block Diagram
04633-033
VX5
In the sample application shown in Figure 25, the timeout nextstate transition is from the EN3V3 and EN2V5 states. For the
EN3V3 state, the signal 3V3ON is asserted on the PDO1 output
pin upon entry to this state to turn on a 3.3 V supply. This supply
rail is connected to the VP2 pin, and the sequence detector looks
for the VP2 pin to go above its undervoltage threshold, which is
set in the supply fault detector (SFD) attached to that pin.
The ADM1064 also has a number of status registers. These include
more detailed information, such as whether an undervoltage or
overvoltage fault is present on a particular input. The status
registers also include information on ADC limit faults. Note that
the data in the status registers is not latched in any way and,
therefore, is subject to change at any time.
See the AN-698 Application Note at www.analog.com for full
details about the ADM1064 registers.
Rev. C | Page 19 of 32
ADM1064
VOLTAGE READBACK
The ADM1064 has an on-board 12-bit accurate ADC for
voltage readback over the SMBus. The ADC has a 12-channel
analog mux on the front end. The 12 channels consist of the
10 SFD inputs (VH, VPx, and VXx) and two auxiliary (singleended) ADC inputs (AUX1 and AUX2). Any or all of these
inputs can be selected to be read, in turn, by the ADC. The
circuit controlling this operation is called the round-robin
circuit. This circuit can be selected to run through its loop of
conversions once or continuously. Averaging is also provided
for each channel. In this case, the round-robin circuit runs through
its loop of conversions 16 times before returning a result for each
channel. At the end of this cycle, the results are written to the
output registers.
The ADC samples single-sided inputs with respect to the
AGND pin. A 0 V input gives out Code 0, and an input equal to
the voltage on REFIN gives out full code (4095 decimal).
The inputs to the ADC come directly from the VXx pins and
from the back of the input attenuators on the VPx and VH pins,
as shown in Figure 27 and Figure 28.
DIGITIZED
VOLTAGE
READING
NO ATTENUATION
12-BIT
ADC
VXx
Table 9. ADC Input Voltage Ranges
SFD Input
Range (V)
0.573 to 1.375
1.25 to 3.00
2.5 to 6.0
6.0 to 14.4
Attenuation Factor
1
2.181
4.363
10.472
ADC Input Voltage
Range (V)
0 to 2.048
0 to 4.46
0 to 6.01
0 to 14.41
1
The upper limit is the absolute maximum allowed voltage on the VPx and
VH pins.
The typical way to supply the reference to the ADC on the
REFIN pin is to connect the REFOUT pin to the REFIN pin.
REFOUT provides a 2.048 V reference. As such, the supervising
range covers less than half the normal ADC range. It is possible,
however, to provide the ADC with a more accurate external
reference for improved readback accuracy.
Supplies can also be connected to the input pins purely for ADC
readback, even though these pins may go above the expected
supervisory range limits (but not above the absolute maximum
ratings on these pins). For example, a 1.5 V supply connected to
the VX1 pin can be correctly read out as an ADC code of approximately 3/4 full scale, but it always sits above any supervisory limits
that can be set on that pin. The maximum setting for the REFIN
pin is 2.048 V.
04633-025
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2.048V VREF
SUPPLY SUPERVISION WITH THE ADC
Figure 27. ADC Reading on VXx Pins
ATTENUATION NETWORK
(DEPENDS ON RANGE SELECTED)
VPx/VH
DIGITIZED
VOLTAGE
READING
2.048V VREF
04633-026
12-BIT
ADC
Figure 28. ADC Reading on VPx/VH Pins
The voltage at the input pin can be derived from the following
equation:
V=
ADC Code
4095
× Attenuation Factor × VREFIN
where VREFIN = 2.048 V when the internal reference is used (that
is, the REFIN pin is connected to the REFOUT pin).
The ADC input voltage ranges for the SFD input ranges are
listed in Table 9.
In addition to the readback capability, another level of supervision is provided by the on-chip, 12-bit ADC. The ADM1064 has
limit registers with which the user can program a maximum or
minimum allowable threshold. Exceeding the threshold generates
a warning that can either be read back from the status registers
or input into the SE to determine what sequencing action the
ADM1064 should take. Only one register is provided for each input
channel. Therefore, either an undervoltage threshold or overvoltage
threshold (but not both) can be set for a given channel. The roundrobin circuit can be enabled via an SMBus write, or it can be
programmed to turn on in any state in the SE program. For
example, it can be set to start after a power-up sequence is
complete, and all supplies are known to be within expected
tolerance limits.
Note that a latency is built into this supervision, dictated by the
conversion time of the ADC. With all 12 channels selected, the
total time for the round-robin operation (averaging off) is
approximately 6 ms (500 μs per channel selected). Supervision
using the ADC, therefore, does not provide the same real-time
response as the SFDs.
Rev. C | Page 20 of 32
ADM1064
APPLICATIONS DIAGRAM
12V IN
12V OUT
5V IN
5V OUT
3V IN
3V OUT
IN
DC-TO-DC1
VH
5V OUT
3V OUT
3.3V OUT
2.5V OUT
1.8V OUT
1.2V OUT
0.9V OUT
POWRON
EN
OUT
3.3V OUT
ADM1064
VP1
VP2
VP3
VP4
VX1
VX2
VX3
PDO1
PDO2
VX4
PDO6
IN
DC-TO-DC2
PDO3
PDO4
PDO5
RESET
PDO7
VX5
PDO8
PDO9
PDO10
REFOUT
EN
OUT
2.5V OUT
PWRGD
SIGNAL VALID
IN
SYSTEM RESET
DC-TO-DC3
EN
OUT
1.8V OUT
3.3V OUT
REFIN VCCP VDDCAP GND
IN
LDO
10µF
10µF
10µF
EN
OUT
0.9V OUT
3.3V OUT
IN
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EN
OUT
Figure 29. Applications Diagram
Rev. C | Page 21 of 32
1.2V OUT
04633-068
DC-TO-DC4
ADM1064
COMMUNICATING WITH THE ADM1064
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1064 (undervoltage/overvoltage
thresholds, glitch filter timeouts, PDO configurations, and so on)
is dictated by the contents of the RAM. The RAM comprises
digital latches that are local to each of the functions on the device.
The latches are double-buffered and have two identical latches,
Latch A and Latch B. Therefore, when an update to a function
occurs, the contents of Latch A are updated first, and then the
contents of Latch B are updated with identical data. The advantages
of this architecture are explained in detail in the Updating the
Configuration section.
The two latches are volatile memory and lose their contents at
power-down. Therefore, the configuration in the RAM must be
restored at power-up by downloading the contents of the
EEPROM (nonvolatile memory) to the local latches. This
download occurs in steps, as follows:
1.
2.
3.
4.
5.
6.
With no power applied to the device, the PDOx pins are all
high impedance.
When 1.2 V appears on any of the inputs connected to the
VDD arbitrator (VH or VPx), the PDOx pins are all weakly
pulled to GND with a 20 kΩ resistor.
When the supply rises above the undervoltage lockout of
the device (UVLO is 2.5 V), the EEPROM starts to
download to the RAM.
The EEPROM downloads its contents to all Latch As.
When the contents of the EEPROM are completely
downloaded to the Latch As, the device controller signals
all Latch As to download to all Latch Bs simultaneously,
completing the configuration download.
At 0.5 ms after the configuration download completes, the first
state definition is downloaded from the EEPROM into the SE.
The ADM1064 provides several options that allow the user to
update the configuration over the SMBus interface. The following
three options are controlled in the UPDCFG register:
Option 1
Update the configuration in real time. The user writes to the
RAM across the SMBus, and the configuration is updated
immediately.
Option 2
Update the Latch As without updating the Latch Bs. With this
method, the configuration of the ADM1064 remains unchanged
and continues to operate in the original setup until the instruction
is given to update the Latch Bs.
Option 3
Change the EEPROM register contents without changing the RAM
contents, and then download the revised EEPROM contents to the
RAM registers. With this method, the configuration of the
ADM1064 remains unchanged and continues to operate in the
original setup until the instruction is given to update the RAM.
The instruction to download from the EEPROM in Option 3 is
also a useful way to restore the original EEPROM contents if
revisions to the configuration are unsatisfactory. For example,
if the user needs to alter an overvoltage threshold, the RAM
register can be updated, as described in Option 1. However,
if the user is not satisfied with the change and wants to revert to
the original programmed value, the device controller can issue
a command to download the EEPROM contents to the RAM
again, as described in Option 3, restoring the ADM1064 to its
original configuration.
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Note that any attempt to communicate with the device prior to
the completion of the download causes the ADM1064 to issue
a no acknowledge (NACK).
UPDATING THE CONFIGURATION
After power-up, with all the configuration settings loaded from
the EEPROM into the RAM registers, the user may need to alter
the configuration of functions on the ADM1064, such as changing
the undervoltage or overvoltage limit of an SFD, changing the
fault output of an SFD, or adjusting the rise time delay of one of
the PDOs.
The topology of the ADM1064 makes this type of operation
possible. The local, volatile registers (RAM) are all doublebuffered latches. Setting Bit 0 of the UPDCFG register to 1 leaves
the double-buffered latches open at all times. If Bit 0 is set to 0
when a RAM write occurs across the SMBus, only the first side
of the double-buffered latch is written to. The user must then
write a 1 to Bit 1 of the UPDCFG register. This generates a pulse
to update all the second latches at once. EEPROM writes occur
in a similar way.
The final bit in this register can enable or disable EEPROM
page erasure. If this bit is set high, the contents of an EEPROM
page can all be set to 1. If this bit is set low, the contents of a
page cannot be erased, even if the command code for page
erasure is programmed across the SMBus. The bit map for the
UPDCFG register is shown in the AN-698 Application Note at
www.analog.com. A flow diagram for download at power-up and
subsequent configuration updates is shown in Figure 30.
Rev. C | Page 22 of 32
ADM1064
SMBus
E
E
P
R
O
M
L
D
DEVICE
CONTROLLER
R
A
M
L
D
D
A
T
A
U
P
D
LATCH A
LATCH B
EEPROM
FUNCTION
(OV THRESHOLD
ON VP1)
04633-035
POWER-UP
(VCC > 2.5V)
Figure 30. Configuration Update Flow Diagram
UPDATING THE SEQUENCING ENGINE
Sequencing engine (SE) functions are not updated in the same
way as regular configuration latches. The SE has its own dedicated
512-byte nonvolatile, electrically erasable, programmable, readonly memory (EEPROM) for storing state definitions, providing
63 individual states, each with a 64-bit word (one state is reserved).
At power-up, the first state is loaded from the SE EEPROM into
the engine itself. When the conditions of this state are met, the
next state is loaded from the EEPROM into the engine, and so
on. The loading of each new state takes approximately 10 μs.
To alter a state, the required changes must be made directly to
the EEPROM. RAM for each state does not exist. The relevant
alterations must be made to the 64-bit word, which is then
uploaded directly to the EEPROM.
The major differences between the EEPROM and other registers
are as follows:
•
•
•
An EEPROM location must be blank before it can be
written to. If it contains data, the data must first be erased.
Writing to the EEPROM is slower than writing to the RAM.
Writing to the EEPROM should be restricted because it has
a limited write/cycle life of typically 10,000 write operations,
due to the usual EEPROM wear-out mechanisms.
The first EEPROM is split into 16 (0 to 15) pages of 32 bytes
each. Page 0 to Page 6, starting at Address 0xF800, hold the
configuration data for the applications on the ADM1064 (such
as the SFDs and PDOs). These EEPROM addresses are the same
as the RAM register addresses, prefixed by F8. Page 7 is
reserved. Page 8 to Page 15 are for customer use.
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INTERNAL REGISTERS
The ADM1064 contains a large number of data registers. The
principal registers are the address pointer register and the
configuration registers.
Data can be downloaded from the EEPROM to the RAM in one
of the following ways:
•
•
Address Pointer Register
The address pointer register contains the address that selects
one of the other internal registers. When writing to the ADM1064,
the first byte of data is always a register address that is written
to the address pointer register.
At power-up, when Page 0 to Page 6 are downloaded
By setting Bit 0 of the UDOWNLD register (0xD8), which
performs a user download of Page 0 to Page 6
SERIAL BUS INTERFACE
The configuration registers provide control and configuration
for various operating parameters of the ADM1064.
The ADM1064 is controlled via the serial system management
bus (SMBus) and is connected to this bus as a slave device under
the control of a master device. It takes approximately 1 ms after
power-up for the ADM1064 to download from its EEPROM.
Therefore, access to the ADM1064 is restricted until the
download is complete.
EEPROM
Identifying the ADM1064 on the SMBus
The ADM1064 has two 512-byte cells of nonvolatile EEPROM
from Register Address 0xF800 to Register Address 0xFBFF. The
EEPROM is used for permanent storage of data that is not lost
when the ADM1064 is powered down. One EEPROM cell contains
the configuration data of the device; the other contains the state
definitions for the SE. Although referred to as read-only memory,
the EEPROM can be written to, as well as read from, using the
serial bus in exactly the same way as the other registers.
The ADM1064 has a 7-bit serial bus slave address (see Table 10).
The device is powered up with a default serial bus address. The
five MSBs of the address are set to 01001; the two LSBs are
determined by the logical states of Pin A1 and Pin A0. This
allows the connection of four ADM1064s to one SMBus.
Configuration Registers
Table 10. Serial Bus Slave Address
A1 Pin
Low
Low
High
High
1
A0 Pin
Low
High
Low
High
Hex Address
0x48
0x4A
0x4C
0x4E
7-Bit Address
0100100x1
0100101x1
0100110x1
0100111x1
x = Read/Write bit. The address is shown only as the first 7 MSBs.
Rev. C | Page 23 of 32
ADM1064
The device also has several identification registers (read-only)
that can be read across the SMBus. Table 11 lists these registers
with their values and functions.
All other devices on the bus remain idle while the selected device
waits for data to be read from or written to it. If the R/W bit is
a 0, the master writes to the slave device. If the R/W bit is a 1, the
master reads from the slave device.
Table 11. Identification Register Values and Functions
Name
MANID
Address
0xF4
Value
0x41
REVID
MARK1
MARK2
0xF5
0xF6
0xF7
0x02
0x00
0x00
Step 2
Function
Manufacturer ID for Analog
Devices
Silicon revision
Software brand
Software brand
Data is sent over the serial bus in sequences of nine clock pulses:
eight bits of data followed by an acknowledge bit from the slave
device. Data transitions on the data line must occur during the
low period of the clock signal and remain stable during the high
period because a low-to-high transition when the clock is high
could be interpreted as a stop signal. If the operation is a write
operation, the first data byte after the slave address is a command
byte. This command byte tells the slave device what to expect next.
It may be an instruction telling the slave device to expect a block
write, or it may be a register address that tells the slave where
subsequent data is to be written. Because data can flow in only
one direction, as defined by the R/W bit, sending a command to
a slave device during a read operation is not possible. Before a
read operation, it may be necessary to perform a write operation
to tell the slave what sort of read operation to expect and/or the
address from which data is to be read.
General SMBus Timing
Figure 31, Figure 32, and Figure 33 are timing diagrams for
general read and write operations using the SMBus. The SMBus
specification defines specific conditions for different types of
read and write operations, which are discussed in the Write
Operations and Read Operations sections.
The general SMBus protocol operates as follows:
Step 1
The master initiates data transfer by establishing a start condition,
defined as a high-to-low transition on the serial data line SDA,
while the serial clock-line SCL remains high. This indicates that
a data stream follows. All slave peripherals connected to the serial
bus respond to the start condition and shift in the next eight bits,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
Step 3
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line high
during the 10th clock pulse to assert a stop condition. In read
mode, the master device releases the SDA line during the low
period before the ninth clock pulse, but the slave device does
not pull it low. This is known as a no acknowledge (NACK).
The master then takes the data line low during the low period
before the 10th clock pulse, and then high during the 10th clock
pulse to assert a stop condition.
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The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and by holding it low during the high period of this clock pulse.
1
9
1
9
SCL
1
0
0
1
A1
A0
D7
R/W
D6
D5
SDA
(CONTINUED)
D3
D2
D1
FRAME 2
COMMAND CODE
1
D7
9
D6
D5
D4
D3
D0
ACK. BY
SLAVE
FRAME 1
SLAVE ADDRESS
SCL
(CONTINUED)
D4
ACK. BY
SLAVE
START BY
MASTER
D2
FRAME 3
DATA BYTE
D1
D0
1
D7
ACK. BY
SLAVE
9
D6
D5
D4
D2
FRAME N
DATA BYTE
Figure 31. General SMBus Write Timing Diagram
Rev. C | Page 24 of 32
D3
D1
D0
ACK. BY
SLAVE
STOP
BY
MASTER
04633-036
0
SDA
ADM1064
1
9
1
9
SCL
1
0
0
1
A1
A0 R/W
D7
D6
D5
D4
D3
D2
D1
ACK. BY
SLAVE
START BY
MASTER
1
SCL
(CONTINUED)
SDA
(CONTINUED)
D7
FRAME 1
SLAVE ADDRESS
D6
D5
D4
D3
9
D2
FRAME 3
DATA BYTE
D1
D0
ACK. BY
MASTER
D0
1
D7
FRAME 2
DATA BYTE
D6
D5
ACK. BY
MASTER
D4
9
D3
D2
FRAME N
DATA BYTE
D1
D0
NO ACK.
STOP
BY
MASTER
Figure 32. General SMBus Read Timing Diagram
tR
tF
t HD; STA
t LO W
SCL
t HI G H
t HD; STA
t HD; DAT
t SU; STA
t SU; STO
t SU; DAT
t BUF
P
S
S
Figure 33. Serial Bus Timing Diagram
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Rev. C | Page 25 of 32
P
04633-038
SDA
04633-037
0
SDA
ADM1064
•
The ADM1064 contains volatile registers (RAM) and nonvolatile
registers (EEPROM). User RAM occupies Address 0x00 to
Address 0xDF; the EEPROM occupies Address 0xF800 to
Address 0xFBFF.
Data can be written to and read from both the RAM and the
EEPROM as single data bytes. Data can be written only to
unprogrammed EEPROM locations. To write new data to a
programmed location, the location contents must first be erased.
EEPROM erasure cannot be done at the byte level. The EEPROM
is arranged as 32 pages of 32 bytes each, and an entire page must
be erased.
The master sends a command code telling the slave device to
erase the page. The ADM1064 command code for a page
erasure is 0xFE (1111 1110). Note that for a page erasure to
take place, the page address must be given in the previous
write word transaction (see the Write Byte/Word section).
In addition, Bit 2 in the UPDCFG register (Address 0x90)
must be set to 1.
Page erasure is enabled by setting Bit 2 in the UPDCFG register
(Address 0x90) to 1. If this bit is not set, page erasure cannot occur,
even if the command byte (0xFE) is programmed across the
SMBus.
1
S
In the ADM1064, the write byte/word protocol is used for three
purposes:
•
S
W
3
4
5
6
A
RAM
ADDRESS
(0x00 TO 0xDF)
A
P
To write a single byte of data to the RAM. In this case, the
command byte is RAM Address 0x00 to RAM Address 0xDF,
and the only data byte is the actual data, as shown in Figure 36.
1
2
3
4
5
6
7 8
RAM
SLAVE W A
S ADDRESS
ADDRESS
A DATA A P
(0x00 TO 0xDF)
Figure 36. Single Byte Write to the RAM
04633-039
2
P
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts an ACK on SDA.
4. The master sends a command code.
5. The slave asserts an ACK on SDA.
6. The master sends a data byte.
7. The slave asserts an ACK on SDA.
8. The master sends a data byte or asserts a stop condition.
9. The slave asserts an ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
To write a register address to the RAM for a subsequent
single byte read from the same address, or for a block read
or a block write starting at that address, as shown in Figure 34.
SLAVE
ADDRESS
A
Figure 34. Setting a RAM Address for Subsequent Read
Rev. C | Page 26 of 32
04633-041
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an acknowledge (ACK)
on SDA.
The master sends a command code.
The slave asserts an ACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
1
A
1.
2.
In the ADM1064, the send byte protocol is used for two
purposes:
•
6
In a write byte/word operation, the master device sends a
command byte and one or two data bytes to the slave device,
as follows:
In a send byte operation, the master device sends a single
command byte to a slave device, as follows:
4.
5.
6.
5
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Send Byte
3.
W
4
COMMAND
BYTE
(0xFE)
Write Byte/Word
The ADM1064 uses the following SMBus write protocols.
1.
2.
SLAVE
ADDRESS
3
As soon as the ADM1064 receives the command byte,
page erasure begins. The master device can send a stop
command as soon as it sends the command byte. Page
erasure takes approximately 20 ms. If the ADM1064 is
accessed before erasure is complete, it responds with a
no acknowledge (NACK).
The SMBus specification defines several protocols for different
types of read and write operations. The following abbreviations
are used in Figure 34 to Figure 42:
S = Start
P = Stop
R = Read
W = Write
A = Acknowledge
A = No acknowledge
2
Figure 35. EEPROM Page Erasure
WRITE OPERATIONS
•
•
•
•
•
•
To erase a page of EEPROM memory. EEPROM memory
can be written to only if it is unprogrammed. Before writing
to one or more EEPROM memory locations that are already
programmed, the page(s) containing those locations must
first be erased. EEPROM memory is erased by writing a
command byte.
04633-040
SMBus PROTOCOLS FOR RAM AND EEPROM
ADM1064
1
2
3
4
5
7 8
6
EEPROM
EEPROM
SLAVE
ADDRESS
ADDRESS
S ADDRESS W A
A
A P
HIGH BYTE
LOW BYTE
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
7.
8.
9.
10.
1
S
2
3
SLAVE
S ADDRESS W A
4
5
6
7
8
9 10
EEPROM
EEPROM
ADDRESS
ADDRESS
P
A
HIGH BYTE
LOW BYTE A DATA A
(0xF8 TO 0xFB)
(0x00 TO 0xFF)
04633-043
2
Figure 38. Single Byte Write to the EEPROM
Block Write
4
5
6
8
7
9
10
Figure 39. Block Write to the EEPROM or RAM
To write a single byte of data to the EEPROM. In this case,
the command byte is the high byte of EEPROM Address
0xF8 to EEPROM Address 0xFB. The first data byte is the
low byte of the EEPROM address, and the second data byte
is the actual data, as shown in Figure 38.
1
3
SLAVE
W A COMMAND 0xFC A BYTE A DATA A DATA A DATA A P
ADDRESS
(BLOCK WRITE)
COUNT
1
2
N
Figure 37. Setting an EEPROM Address
Because a page consists of 32 bytes, only the three MSBs of
the address low byte are important for page erasure. The
lower five bits of the EEPROM address low byte specify the
addresses within a page and are ignored during an erase
operation.
•
The slave asserts an ACK on SDA.
The master sends N data bytes.
The slave asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except when
•
•
There must be at least N locations from the start address to
the highest EEPROM address (0xFBFF) to avoid writing to
invalid addresses.
An address crosses a page boundary. In this case, both
pages must be erased before programming.
Note that the ADM1064 features a clock extend function for
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1064 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
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READ OPERATIONS
In a block write operation, the master device writes a block of
data to a slave device. The start address for a block write must
have been set previously. In the ADM1064, a send byte operation sets a RAM address, and a write byte/word operation sets
an EEPROM address, as follows:
The ADM1064 uses the following SMBus read protocols.
1.
2.
1.
2.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by
the write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block write. The ADM1064 command
code for a block write is 0xFC (1111 1100).
The slave asserts ACK on SDA.
The master sends a data byte that tells the slave device how
many data bytes are being sent. The SMBus specification
allows a maximum of 32 data bytes in a block write.
Receive Byte
In a receive byte operation, the master device receives a single
byte from a slave device, as follows:
3.
4.
5.
6.
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
transaction ends.
In the ADM1064, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation, as shown in Figure 40.
1
2
S
SLAVE
ADDRESS
R
3
4
5
6
A
DATA
A
P
04633-045
3.
4.
04633-044
To set up a 2-byte EEPROM address for a subsequent read,
write, block read, block write, or page erase. In this case, the
command byte is the high byte of EEPROM Address 0xF8
to EEPROM Address 0xFB. The only data byte is the low
byte of the EEPROM address, as shown in Figure 37.
04633-042
•
Figure 40. Single Byte Read from the EEPROM or RAM
Rev. C | Page 27 of 32
ADM1064
Block Read
Error Correction
In a block read operation, the master device reads a block of data
from a slave device. The start address for a block read must have
been set previously. In the ADM1064, this is done by a send byte
operation to set a RAM address, or a write byte/word operation
to set an EEPROM address. The block read operation itself consists
of a send byte operation that sends a block read command to
the slave, immediately followed by a repeated start and a read
operation that reads out multiple data bytes, as follows:
The ADM1064 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
that the data received by or sent from the ADM1064 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1064. The protocol is the
same as a block read for Step 1 to Step 12 and then proceeds as
follows:
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
1
The master device asserts a start condition on SDA.
The master sends the 7-bit slave address followed by the
write bit (low).
The addressed slave device asserts an ACK on SDA.
The master sends a command code that tells the slave
device to expect a block read. The ADM1064 command
code for a block read is 0xFD (1111 1101).
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
The slave asserts an ACK on SDA.
The ADM1064 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1064
always returns 32 data bytes (0x20), which is the maximum
allowed by the SMBus Version 1.1 specification.
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end the
transaction.
13. The ADM1063 issues a PEC byte to the master. The master
checks the PEC byte and issues another block read if the
PEC byte is incorrect.
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end the
transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C(x) = x8 + x2 + x1 + 1
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
in Figure 42.
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2
3
4
5 6
7
8
9
10
11
1
3
4
5 6
7
8
9
10
11
13 14 15
DATA
32
A PEC A P
Figure 42. Block Read from the EEPROM or RAM with PEC
SLAVE
COMMAND 0xFD
SLAVE
BYTE
DATA
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
A
1
04633-046
13
P
12
SLAVE
SLAVE
BYTE
DATA
COMMAND 0xFD
A
S ADDRESS W A (BLOCK READ) A S ADDRESS R A COUNT A
1
12
DATA A
32
2
Figure 41. Block Read from the EEPROM or RAM
Rev. C | Page 28 of 32
04633-047
1.
2.
ADM1064
OUTLINE DIMENSIONS
6.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
31
30
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
5.75
BCS SQ
4.25
4.10 SQ
3.95
(BOT TOM VIEW)
21
20
10
11
0.25 MIN
4.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
101306-A
1.00
0.85
0.80
1
EXPOSED
PAD
0.50
0.40
0.30
12° MAX
40
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 43. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6 mm × 6 mm Body, Very Thin Quad
(CP-40-1)
Dimensions shown in millimeters
0.75
0.60
0.45
1.20
MAX
9.00
BSC SQ
37
36
48
1
www.BDTIC.com/ADI
PIN 1
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
7.00
BSC SQ
TOP VIEW
0° MIN
(PINS DOWN)
12
13
25
24
VIEW A
0.50
0.27
BSC
0.22
LEAD PITCH
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABC
Figure 44. 48-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1064ACP
ADM1064ACP-REEL
ADM1064ACP-REEL7
ADM1064ACPZ 1
ADM1064ASU
ADM1064ASU-REEL
ADM1064ASU-REEL7
ADM1064ASUZ1
EVAL-ADM1064LFEBZ1
EVAL-ADM1064TQEBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
40-Lead LFCSP_VQ
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
48-Lead TQFP
Evaluation Kit [LFCSP Version]
Evaluation Kit [TQFP Version]
Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
Package Option
CP-40-1
CP-40-1
CP-40-1
CP-40-1
SU-48
SU-48
SU-48
SU-48
ADM1064
NOTES
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Rev. C | Page 30 of 32
ADM1064
NOTES
www.BDTIC.com/ADI
Rev. C | Page 31 of 32
ADM1064
NOTES
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©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04633-0-5/08(C)
Rev. C | Page 32 of 32