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SN65MLVD128
SN65MLVD129
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SLLS586 – MARCH 2004
1:8 LVTTL TO M-LVDS REPEATER DUAL 1:4 LVTTL TO M-LVDS REPEATER
•
FEATURES
•
•
•
•
•
•
(1)
LVTTL Receiver and Eight Line Drivers
Configured as an 8-Port M-LVDS Repeater –
SN65MLVD128
2 LVTTL Receivers and Eight Line Drivers
Configured as Dual 4-Port M-LVDS Repeaters
– SN65MLVD129
Drivers Meet or Exceed the M-LVDS Standard
(TIA/EIA-899)
Low-Voltage Differential 30-Ω to 55-Ω Line
Drivers for Data Rates (1) Up to 250 Mbps or
Clock Frequencies Up to 125 MHz
Power Up/Down Glitch Free
Controlled Driver Output Voltage Transition
Times for Improved Signal Quality
The data rate of a line, is the number of voltage transitions
that are made per second expressed in the units bps (bits per
second).
Bus Pins High Impedance When Disabled or
VCC ≤ 1.5 V
Independent Enables for each Driver
Output-to-Ouput Skew tsk(o) ≤ 160 ps
Part-to-Part Skew tsk(pp) ≤ 800 ps
Single 3.3-V Voltage Supply
Bus Pin ESD Protection Exceeds 9 kV
Packaged in 48-Pin TSSOP (DGG)
•
•
•
•
•
APPLICATIONS
•
•
•
AdvancedTCA™ (ATCA™) Clock Bus Driver
Clock Distribution
Data and Clock Repeating Over Backplanes
and Cables
Cellular Base Stations
Central Office Switches
Network Switches and Routers
•
•
•
LOGIC DIAGRAM
1NE
1NE
A1
A1
B1
2NE
B1
2NE
A2
B2
3NE
A3
A2
B2
D1
3NE
A3
B3
4NE
A4
B4
D1
B3
4NE
A4
B4
5NE
5NE
A5
A5
B5
B5
6NE
6NE
A6
B6
A6
B6
7NE
A7
D2
7NE
A7
B7
8NE
B7
8NE
A8
B8
LM56NS 821DV
A8
B8
LM56NS 921DV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
AdvancedTCA, ATCA are trademarks of PCI Industrial Computer Manufacturers Group.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
SN65MLVD128
SN65MLVD129
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SLLS586 – MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION
The SN65MLVD128 and SN65MLVD129 are LVTTL-to-M-LVDS translators/repeaters. Outputs comply with the
M-LVDS standard (TIA/EIA-899) and are optimized for data rates up to 250 Mbps, and clock frequencies up to
125 MHz. The driver outputs have been designed to support multipoint buses presenting loads as low as 30 Ω
and incorporates controlled transition times for backbone operation.
M-LVDS compliant devices allow for 32 nodes on a common bus, providing a high-speed replacement for
RS-485 devices when lower common-mode voltage range and lower output signaling levels are acceptable. The
SN65MLVD128 and SN65MLVD129 provide separate driver enables, allowing for independent control of each
output signal.
Intended applications for these devices include transmission of clock signals from a central clock module, as well
as translation and buffering of data or control signals for transmission through a controlled impedance backplane
or cable.
ORDERING INFORMATION
PART NUMBER
INPUT/OUTPUT CHANNEL
PART MARKING
PACKAGE/CARRIER
SN65MLVD128DGG
1:8
MLVD128
48-Pin TSSOP/Tube
SM65MLVD128DGGR
1:8
MLVD128
48-Pin TSSOP/Tape and Reeled
SN65MLVD129DGG
Dual 1:4
MLVD129
48-Pin TSSOP/Tube
SM65MLVD129DGGR
Dual 1:4
MLVD129
48-Pin TSSOP/Tape and Reeled
PACKAGE DISSIPATION RATINGS
PACKAGE
PCB JEDEC
STANDARD
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
48-DGG
Low-K (2)
1114.6 mW
9.7 mW/°C
533.1 mW
48-DGG
High-K (3)
1824.5 mW
15.9 mW/°C
872.6 mw
(1)
(2)
(3)
This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1)
SN65MLVD128, 129
range (2)
VCC
Supply voltage
VI
Input voltage range
D, EN
–0.5 V to 4 V
–0.5 V to 4 V
VO
Output voltage range
A or B
–1.8 V to 4 V
Human Body Model (3)
Electrostatic discharge
All pins
±4 kV
Charged-Device Model (4)
All pins
±1500 V
Machine Model (5)
All pins
200 V
Continuous power dissipation
(1)
(2)
(3)
(4)
(5)
2
±9 kV
A, B
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-B.
Tested in accordance with JEDEC Standard 22, Test Method C101-A.
Tested in accordance with JEDEC Standard 22, Test Method A115-A.
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SN65MLVD128
SN65MLVD129
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RECOMMENDED OPERATING CONDITIONS
MIN
NOM
3.3
MAX
VCC
Supply voltage
3
VIH
High-level input voltage (1)
2
VCC
V
VIL
Low-level input voltage (2)
0
0.8
V
–1.4
3.8
V
30
55
Ω
250
Mbps
125
MHz
85
°C
Voltage at any bus terminal (separate or common mode) VA or VB
RL
Differential load resistance
1/tUI
Signaling rate
Clock frequency
TA
(1)
(2)
Ambient temperature
–40
3.6
UNIT
V
In accordance with the High-K thermal metric difinitions of EIA/JESD51-7.
In accordance with the Low-K thermal metric difinitions of EIA/JESD51-3.
DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
Driver enabled
ICC
Supply current
Driver disabled
PD
(1)
(2)
Device power dissipation
TEST CONDITIONS
MIN (1) TYP (2) MAX
EN = VCC, Input = VCC or GND, RL = 50 Ω
EN = VCC, Input = VCC or GND, RL = No load
112
UNIT
140
mA
45
mA
EN = VCC, Input = VCC or GND, RL = 50 Ω
7
mA
EN = VCC, Input = VCC or GND, RL = No load
7
mA
529
mW
VCC = 3.6 V, EN = VCC, CL = 15 pF, RL = 50 Ω,
Input 125 MHz 50 % duty cycle square wave, TA = 85°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
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DEVICE ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN (1) TYP (2)
MAX
UNIT
LVTTL (D, EN) INPUT SPECIFICATIONS
|IIH|
High-level input current
VIH = 2 V or VCC
|IIL|
Low-level input current
VIL = GND or 0.8 V
Ci
Input capacitance
VI = 0.4 sin(30E6πt) + 0.5 V (3)
10
µA
10
µA
5
pF
M-LVDS (A, B) OUTPUT SPECIFICATIONS
|VAB|
Differential output voltage magnitude
480
650
mV
∆|VAB|
Change in differential output voltage magnitude See Figure 2
between logic states
–50
50
mV
VOS(SS)
Steady-state common-mode output voltage
0.8
1.2
V
-50
50
mV
150
mV
0
2.4
V
0
2.4
V
1.2
VSS
V
∆VOS(SS Change in steady-state common-mode output
voltage between logic states
)
VOS(PP)
Peak-to-peak common-mode output voltage
VA(OC)
Maximum steady-state open-circuit output
voltage
See Figure 3
See Figure 7
VB(OC)
Maximum steady-state open-circuit output
voltage
VP(H)
Voltage overshoot, low-to-high level output
VP(L)
Voltage overshoot, high-to-low level output
|IOS|
Differential short-circuit output current
magnitude
See Figure 4
IOZ
High-impedance state output current
–1.4 V ≤ (VA or VB) ≤ 3.8 V,
Other output = 1.2 V
IO(OFF)
Power-off output current
–1.4 V ≤ (VA or VB) ≤ 3.8 V,
Other output = 1.2 V, 0 ≤ VCC≤ 1.5 V
See Figure 5
–0.2 VSS
CA orCB Output capacitance
VI = 0.4 sin(30E6πt) + 0.5 V, (3)
Other input at 1.2 V, driver disabled
CAB
Differential output capacitance
VI = 0.4 sin(30E6πt) V,
Driver disabled
CA/B
Output capacitance balance, (CA/CB)
(1)
(2)
(3)
4
V
24
mA
–20
20
µA
–20
20
µA
3
pF
(3)
2.5
0.99
1.01
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
All typical values are at 25°C and with a 3.3-V supply voltage.
HP4194A impedance analyzer (or equivalent)
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SN65MLVD129
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SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
See Figure 5
MIN TYP (1) MAX
UNIT
1
3
ns
1
3
ns
tr
Differential output signal rise time
1
2
ns
tf
Differential output signal fall time
1
2
ns
tsk(p)
Pulse skew (|tpHL– tpLH|)
100
ps
tsk(o)
Output skew
160
ps
tsk(bb)
Bank-to-bank skew (2)
100
ps
tsk(pp)
Part-to-part skew (3)
800
ps
deviation) (4)
tjit(per)
Period jitter, rms (1 standard
tjit(c-c)
Cycle-to-cycle jitter (4)
100 MHz clock input, All channels enabled
tjit(pp)
Peak-to-peak jitter (4)
200 Mbps 215-1 PRBS input, All channels
enabled
tPZH
Enable time, high-impedance-to-high-level output
tPZL
Enable time, high-impedance-to-low-level output
tPHZ
Disable time, high-level-to-high-impedance output
tPLZ
Disable time, low-level-to-high-impedance output
(1)
(2)
(3)
(4)
100 MHz clock input, All channels enabled
See Figure 6
See Figure 6
1
46
3
ps
20
ps
110
ps
7
ns
7
ns
7
ns
7
ns
All typical values are at 25°C and with a 3.3-V supply voltage.
tsk(bb), which only applies to the SN65MLVD129, is the magnitude of the difference between the tPLH and tPHL of two outputs of any
bank.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Stimulus jitter has been subtracted from the numbers.
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SN65MLVD129
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PARAMETER MEASUREMENT INFORMATION
V CC
I
A
A
II
VA+
D
VAB
I
B
B
2
VY
B
V I
VO S
VB
Figure 1. Driver Voltage and Current Definitions
k 23.3
A
VAB
D
9.94
B
Ω
+
_ V 1-
Ω
k 23.3
≤V V
tes4t.≤3
Ω
NOTE: All resistors are 1% tolerance.
Figure 2. Differential Output Voltage Test Circuit
1R
9.42
A
1C
Fp 1
D
V3
≈.1
B
V7
≈.0
VO S P
(P)
B
2C
Fp 1
A
Ω
2R
9.42
Ω
3C
Fp 5.2
VO S
∆VO S S
(S)
VO S S
(S)
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B.
C1, C2 and C3 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C.
R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
D.
The measurement of VOS(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A
V ro V 0
IS
O
CC
+
B
V 4V
.3Treos V
t 1-
Figure 4. Driver Short-Circuit Test Circuit
6
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
VCC/2
Input
0V
tpLH
tpHL
VSS
0.9VSS
VP(H)
Output
0V
VP(L)
0.1V
SS
0 V SS
tf
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
Figure 5. Driver Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
R1
24.9 Ω
A
GND or VCC
Input
C1
1 pF
D
C2
1 pF
B
EN
C4
Output
0.5 pF
R2
24.9 Ω
VCC
VCC/2
0V
EN
tpZH
tpHZ
∼ 0.6 V
0.1 V
0V
Output With
D at VCC
Output With
D at GND
C3
2.5 pF
tpZL
tpLZ
0V
-0.1 V
∼ -0.6 V
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, frequency = 1 MHz,
duty cycle = 50 ± 5%.
B.
C1, C2, C3, and C4 include instrumentation and fixture capacitance within 2 cm of the D.U.T. and are ±20%.
C.
R1 and R2 are metal film, surface mount, ±1%, and located within 2 cm of the D.U.T.
Figure 6. Driver Enable and Disable Time Circuit and Definitions
A
0 V or VCC
B
VA or VB
1.62 kΩ, ±1%
Figure 7. Driver Maximum Steady State Output Voltage
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PARAMETER MEASUREMENT INFORMATION (continued)
VCC
CLOCK
INPUT
VCC/2
0V
1/f0
Period Jitter
IDEAL
OUTPUT 0 V
VCC
PRBS INPUT
VA -VB
0V
ACTUAL
OUTPUT 0 V
VA -VB
VCC/2
1/f0
Peak to Peak Jitter
VA -VB
tc(n)
tjit(per) = tc(n) -1/f0
OUTPUT 0 V
VA -VB
tjit(pp)
Cycle to Cycle Jitter
OUTPUT
0V
VA - VB
tc(n)
tc(n+1)
tjit(cc) = | tc(n) - tc(n+1) |
A.
All input pulses are supplied by an Agilent 8304A Stimulus System.
B.
The measurement is made on a TEK TDS6604 running TDSJIT3 application software
C.
Period jitter and cycle-to-cycle jitter are measured using a 100 MHz 50 ±1% duty cycle clock input.
D.
Peak-to-peak jitter is measured using a 200 Mbps 215-1 PRBS input.
Figure 8. Driver Jitter Measurement Waveforms
8
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Table 1. Terminal Functions
PIN
NAME
TYPE
NO.
DESCRIPTION
SN65MLVD128
1D
39
Input
Data inputs for drivers
EN1–EN8
27, 28, 32, 33, 40, 41, 45, 46
Input
Driver enable, active high, individual enables
1A–8A
2, 4, 8, 10, 14, 16, 20, 22
Output
M-LVDS bus noninverting output
1B–8B
3, 5, 9, 11, 15, 17, 21, 23
Output
M-LVDS bus inverting output
GND
6, 12, 18, 24, 25, 26, 31, 37, 38, 43, 44
Power
Circuit ground
VCC
1, 7, 13, 19, 29, 30, 35, 36, 47, 48
Power
Supply voltage
NC
34, 42
N/A
Not connected
SN65MLVD129
1D, 2D
39, 34
Input
Data inputs for drivers
EN1–EN8
27, 28, 32, 33,40, 41, 45, 46
Input
Driver enable, active high, individual enables
1A–8A
2, 4, 8, 10,14, 16, 20, 22
Output
M-LVDS bus noninverting output
1B–8B
3, 5, 9, 11,15, 17, 21, 23
Output
M-LVDS bus inverting output
GND
6, 12, 18, 24, 25, 26, 31, 37, 38, 43, 44
Power
Circuit ground
VCC
1, 7, 13, 19, 29, 30, 35, 36, 47, 48
Power
Supply voltage
NC
42
N/A
Not connected
PIN ASSIGNMENTS
GGD9L2M
1DV
P POSST-84 EGAKCA
)WEIVTP( O
GGD8L2M
1DV
P POSST-84 EGAKCA
)WEIVTP( O
CCV
A1
B1
A2
B2
DNG
CCV
A3
B3
A4
B4
DNG
CCV
A5
B5
A6
B6
DNG
CCV
A7
B7
A8
B8
DNG
1
2
3
4
5
6
7
8
9
01
11
21
31
41
51
61
71
81
91
02
12
22
32
42
84
74
64
54
44
34
24
14
04
93
83
73
63
53
43
33
23
13
03
92
82
72
62
52
CCV
CCV
1NE
2NE
DNG
DNG
CN
3NE
4NE
D1
DNG
DNG
CCV
CCV
CN
5NE
6NE
DNG
CCV
CCV
7NE
8NE
DNG
DNG
CCV
A1
B1
A2
B2
DNG
CCV
A3
B3
A4
B4
DNG
CCV
A5
B5
A6
B6
DNG
CCV
A7
B7
A8
B8
DNG
1
2
3
4
5
6
7
8
9
01
11
21
31
41
51
61
71
81
91
02
12
22
32
42
84
74
64
54
44
34
24
14
04
93
83
73
63
53
43
33
23
13
03
92
82
72
62
52
CCV
CCV
1NE
2NE
DNG
DNG
CN
3NE
4NE
D1
DNG
DNG
CCV
CCV
D2
5NE
6NE
DNG
CCV
CCV
7NE
8NE
DNG
DNG
noitcennoc lanretni oN - CN
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FUNCTION TABLE
MLVD128 / MLVD129 (1)
(1)
INPUT
ENABLE
D
EN
OUTPUTS
A
B
H
L
H
L
H
H
H
L
OPEN
H
L
H
X
OPEN
Z
Z
X
L
Z
Z
H = high level, L = low level, Z = high impedance, X = Don't care,
OPEN = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
TUPTUO REVIRD
ELBANE REVIRD DNA TUPNI REVIRD
V CC
V CC
004
Ω
NE ro D
ro A
B
V7
k 063
Ω
TYPICAL CHARACTERISTICS
RMS SUPPLY CURRENT
vs
INPUT FREQUENCY
RMS SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
081
081
V3
V.C
3C=
5T
2A=
V = NE llA
0R5 L=
051
V3
V.C
3C=
zHM 001 = f
V = NE llA
0R5 L=
051
C
CC
021
021
09
06
52
05
zHM − ycneuqerF tupnI − f
57
Figure 9.
001
521
Am − tnerruC ylppuS C
SC
M
I R−
Am − tnerruC ylppuS C
SC
M
I R−
09
10
CC
06
04−
51−
53
01
T riA-eerT
FA−− erutarepme
Figure 10.
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06
°C
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TYPICAL CHARACTERISTICS (continued)
DIFFERENTIAL OUTPUT VOLTAGE MAGNITUDE
vs
INPUT FREQUENCY
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
650
2.4
TA = 25C
EN = VCC
RL = 50 ,
2.3
t pd − Propagation Delay Time − ns
VAB − Differential Output Voltage Magnitude − mV
700
600
VCC = 3.6 V
VCC = 3.3 V
550
VCC = 3 V
500
VCC = 3.3 V
f = 500 kHz
EN = VCC
RL = 50 2.2
2.1
tPLH
2
1.9
1.8
tPHL
1.7
450
25
50
75
100
1.6
125
−40
35
Figure 12.
TRANSITION TIME
vs
FREE-AIR TEMPERATURE
PEAK-TO-PEAK JITTER
vs
DATA RATE
60
85
100
VCC = 3.3 V
f = 500 kHz
EN = VCC
RL = 50 90
t jit(p-p) − Peak-To-Peak Jitter − ps
t r or t f − Rising or Falling Transition Time − ns
1.8
10
Figure 11.
2
1.9
−15
TA − Free-Air Temperature − °C
f − Input Frequency − MHz
1.7
1.6
tf
1.5
tr
1.4
1.3
1.2
1.1
80
VCC = 3.3 V,
TA = 25C,
215-1 PRBS NRZ,
All EN = VCC
See Figure 8
70
60
50
40
30
20
1
10
−40
35
−15
60
10
TA − Free-Air Temperature − °C
85
Figure 13.
50
100
150
200
Data Rate − Mbps
250
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
PERIOD JITTER
vs
CLOCK FREQUENCY
CYCLE-TO-CYCLE JITTER
vs
CLOCK FREQUENCY
13
1.0
t jit(per) − Period Jitter − ps
0.8
12
t jit(c-c) − Cycle-To-Cycle Jitter − ps
0.9
VCC = 3.3 V,
TA = 25C,
Input = Clock
All EN = VCC
See Figure 8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
11
10
9
8
7
6
5
4
3
2
1
0
0
25
50
75
100
f − Clock Frequency − MHz
125
25
50
75
100
f − Clock Frequency − MHz
Figure 15.
12
VCC = 3.3 V,
TA = 25C,
Input = Clock
All EN = VCC
See Figure 8
Figure 16.
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Submit Documentation Feedback
125
SN65MLVD128
SN65MLVD129
www.ti.com
SLLS586 – MARCH 2004
APPLICATION INFORMATION
CLOCK DISTRIBUTION
LM56NS 821DVtuptuO
LM56NS 821DVtuptuO
kcolC zHM 8066.9t1u:pencIruoS
V ,elcyC ytuD
= elcyc ytuD tuptuO
m 241 = elacs laciV
tre
1 = elacs latnoziroH
V 3.C
3C=
R 0, 5 L=
%05 htiW kcolC zHM 44.1t6u:pencIruoS
V ,elcyC ytuD
V 3.C
3C=
Fp
C5,.2 L=
R 0, 5 L=
Fp
C5,.2 L=
.%10.05 = elcyc ytud tuptuO
vid/Vm 241 = elacs laciV
tre
vid/sn 4 = elacs latnoziroH
vid/sn 1
Figure 17.
Figure 18.
DATA DISTRIBUTION
LM56NS 821DVtuptuO
2 ,spbM 05t2u:pencIruoS
V3
V.C
3C=
R 0, 5 L=
,SBRP151Fp
C5,.2 L=
vid/Vm 051 = elacs laciV
tre
vid/sn 12.1 = elacs latnoziroH
Figure 19.
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Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65MLVD128DGG
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD128DGGG4
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD128DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD128DGGRG4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD129DGG
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD129DGGG4
ACTIVE
TSSOP
DGG
48
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD129DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
SN65MLVD129DGGRG4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
www.BDTIC.com/TI
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65MLVD128DGGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
SN65MLVD129DGGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
www.BDTIC.com/TI
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65MLVD128DGGR
TSSOP
DGG
48
2000
346.0
346.0
41.0
SN65MLVD129DGGR
TSSOP
DGG
48
2000
346.0
346.0
41.0
www.BDTIC.com/TI
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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