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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 2000 V Per
D
D
D
D
D
D
D
D
D
D
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Meets or Exceeds the Requirements of
ANSI TIA/EIA-644-1995 Standard
Signaling Rates up to 400 Mbps
Bus-Terminal ESD Exceeds 12 kV
Operates From a Single 3.3-V Supply
Low-Voltage Differential Signaling With
Typical Output Voltages of 350 mV and a
100-Ω Load
Propagation Delay Times
− Driver: 1.7 ns Typ
− Receiver: 3.7 ns Typ
Power Dissipation at 200 MHz
− Driver: 25 mW Typical
− Receiver: 60 mW Typical
LVTTL Input Levels Are 5-V Tolerant
Receiver Maintains High Input Impedance
With VCC < 1.5 V
Receiver Has Open-Circuit Fail Safe
description/ordering information
The
SN65LVDS179,
SN65LVDS180,
SN65LVDS050, and SN65LVDS051 are differential line drivers and receivers that use low-voltage
differential signaling (LVDS) to achieve signaling
rates as high as 400 Mbps. The TIA/EIA-644
standard compliant electrical interface provides a
minimum differential output voltage magnitude
of 247 mV into a 100-Ω load and receipt of
50-mV signals with up to 1 V of ground potential
difference between a transmitter and receiver.
SN65LVDS179D
(TOP VIEW)
5
3
VCC
R
D
GND
1
8
2
7
3
6
4
5
A
B
Z
Y
Y
6
D
Z
8
2
A
7
R
B
SN65LVDS180D OR SN65LVDS180PW
(TOP VIEW)
NC
R
RE
DE
D
GND
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
VCC
A
B
Z
Y
NC
10
4
DE
4
13
5
12
6
11
7
10
8
9
1Z
DE
2Z
2Y
2D
12
2
4
13
5
12
6
11
7
10
8
9
1Z
2DE
2Z
2Y
2D
11
R
3
1R
14
13
10
11
2
1
4
RE
6
5
2R
SN65LVDS051D OR SN65LVDS051PW
(TOP VIEW)
15
1D
1B 1
16 VCC
4
1DE
1A 2
15 1D
3
1R 3
1R
14 1Y
1DE
2R
2A
2B
GND
9
2D
7
14
13
2
1
10
11
12
6
2DE
5
2R
Y
Z
3
RE
SN65LVDS050D OR SN65LVDS050PW
15
(TOP VIEW)
1D
12
1B 1
16 VCC
DE
9
1A 2
15 1D
2D
1R 3
14 1Y
RE
2R
2A
2B
GND
9
5
D
7
A
B
1Y
1Z
2Y
2Z
1A
1B
2A
2B
1Y
1Z
1A
1B
2Y
2Z
2A
2B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2008, Texas Instruments Incorporated
This document contains information on products in more than one phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
description/ordering information (continued)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100-Ω characteristic impedance. The transmission media
may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer
is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
application specific characteristics).
The devices offer various driver, receiver, and enabling combinations in industry standard footprints. Since
these devices are intended for use in simplex or distributed simplex bus structures, the driver enable function
does not put the differential outputs into a high-impedance state but rather disconnects the input and reduces
the quiescent power used by the device. (For these functions with a high-impedance driver output, see the
SN65LVDM series of devices.) All devices are characterized for operation from −40°C to 85°C.
ORDERING INFORMATION†
ORDERABLE
PART NUMBER
PACKAGE‡
TA
40°C to 85°C
−40°C
−40°C
40°C to 85°C
40°C to 85°C
−40°C
−40°C
40°C to 85°C
TOP-SIDE
MARKING
SOIC (D)
Tape and Reel
SN65LVDS179DRQ1§
VDS179Q
TSSOP (PW)
Tape and Reel
SN65LVDS179PWRQ1§
VDS179Q
SOIC (D)
Tape and Reel
SN65LVDS180DRQ1
VDS180Q
TSSOP (PW)
Tape and Reel
SN65LVDS180PWRQ1
VDS180Q
SOIC (D)
Tape and Reel
SN65LVDS050DRQ1§
VDS050Q
TSSOP (PW)
Tape and Reel
SN65LVDS050PWRQ1§
VDS050Q
SOIC (D)
Tape and Reel
SN65LVDS051DRQ1
VDS051Q
TSSOP (PW)
Tape and Reel
SN65LVDS051PWRQ1
VDS051Q
†
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§ Product Preview
2
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
Function Tables
SN65LVDS179 RECEIVER
INPUTS
OUTPUT
VID = VA − VB
R
VID ≥ 50 mV
H
−50 mV < VID < 50 mV
?
VID ≤ −50 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
SN65LVDS179 DRIVER
INPUT
OUTPUTS
D
Y
Z
L
L
H
H
H
L
Open
L
H
H = high level, L = low level
SN65LVDS180, SN65LVDS050, and SN65LVDS051 RECEIVER
INPUTS
OUTPUT
VID = VA − VB
RE
R
VID ≥ 50 mV
L
H
−50 mV < VID < 50 mV
L
?
VID ≤ −50 mV
L
L
Open
L
H
X
H
Z
H = high level, L = low level, Z = high impedance,
X = don’t care
SN65LVDS180, SN65LVDS050, and SN65LVDS051 DRIVER
INPUTS
OUTPUTS
D
DE
Y
Z
L
H
L
H
H
H
H
L
Open
H
L
H
X
L
OFF
OFF
H = high level, L = low level, OFF = No Output,
X = don’t care
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
equivalent input and output schematic diagrams
VCC
VCC
VCC
300 kΩ
50 Ω
5Ω
10 kΩ
D or
RE
Input
Y or Z
Output
50 Ω
DE
Input
7V
300 kΩ
7V
7V
VCC
VCC
300 kΩ
300 kΩ
5Ω
A Input
R Output
B Input
7V
7V
7V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Voltage range: D, R, DE, RE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6 V
Y, Z, A, and B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
Electrostatic discharge: Y, Z, A, B , and GND (see Note 2) . . . . . . . . . . . . . . . . . . CLass 3, A:12 kV, B:600 V
All . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3, A:7 kV, B:500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages are with respect to network ground terminal.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
4
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
DISSIPATION RATING TABLE
†
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C†
TA = 85°C
POWER RATING
PW(14)
736 mW
5.9 mW/°C
383 mW
PW(16)
839 mW
6.7 mW/°C
437 mW
D(8)
635 mW
5.1 mW/°C
330 mW/°C
D(14)
987 mW
7.9 mW/°C
513 mW/°C
D(16)
1110 mW
8.9 mW/°C
577 mW/°C
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN
NOM
Supply voltage, VCC
3
3.3
High-level input voltage, VIH
2
MAX
UNIT
3.6
V
V
Low-level input voltage, VIL
0.8
Magnitude of differential input voltage, VID
0.1
Magnitude of differential output voltage with disabled driver, VOD(dis)
Driver output voltage, VOY or VOZ
0
ŤVIDŤ
Common-mode input voltage, VIC (see Figure 5)
0.6
V
520
mV
2.4
V
2.4 *
2
V
ŤVIDŤ
2
V
VCC−0.8
Operating free-air temperature, TA
−40
°C
85
device electrical characteristics over recommended operating conditions (unless otherwise
noted)
TYP†
MAX
No receiver load, driver RL = 100 Ω
9
12
Driver and receiver enabled, no receiver load, driver RL = 100 Ω
9
12
Driver enabled, receiver disabled, RL = 100 Ω
5
7
Driver disabled, receiver enabled, no load
1.5
2
Disabled
0.5
1
Drivers and receivers enabled, no receiver loads, driver RL = 100 Ω
12
20
Drivers enabled, receivers disabled, RL = 100 Ω
10
16
3
6
PARAMETER
SN65LVDS179
SN65LVDS180
ICC
Supply
S
l
current
SN65LVDS050
SN65LVDS051
†
TEST CONDITIONS
MIN
Drivers disabled, receivers enabled, no loads
Disabled
0.5
1
Drivers enabled, no receiver loads, driver RL = 100 Ω
12
20
3
6
Drivers disabled, no loads
UNIT
mA
mA
mA
mA
All typical values are at 25°C and with a 3.3-V supply.
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOD
Differential output voltage magnitude
∆VOD
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode output voltage
RL = 100 Ω
Ω,
See Figures 1 and 2
MIN
TYP
MAX
247
340
454
−50
50
1.125
See Figure 3
1.2
−50
High level input current
High-level
IIL
Low level input current
Low-level
2
20
−0.5
−10
2
10
IOS
Short circuit output current
Short-circuit
VOY or VOZ = 0 V
3
10
VOD = 0 V
3
10
VIL = 0
0.8
8V
D
mV
150
−20
DE
V
mV
50
VIH = 5 V
D
mV
50
−0.5
DE
IIH
1.375
UNIT
µA
A
µA
A
mA
DE = 0 V,
VOY = VOZ = 0 V
IO(OFF)
Off-state output current
CIN
Input capacitance
DE = VCC,
VOY = VOZ = 0 V,
VCC < 1.5 V
−1
1
3
µA
pF
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input voltage threshold
VIT−
Negative-going differential input voltage threshold
VOH
High level output voltage
High-level
VOL
Low-level output voltage
MIN
TYP†
MAX
UNIT
50
See Figure 5 and Table 1
mV
−50
IOH = −8 mA
2.4
IOH = −4 mA
2.8
V
IOL = 8 mA
VI = 0
0.4
−2
−11
−1.2
−3
−20
V
A
µA
II
Input current (A or B inputs)
II(OFF)
Power-off input current (A or B inputs)
VCC = 0
±20
µA
IIH
High-level input current (enables)
VIH = 5 V
±10
µA
IIL
Low-level input current (enables)
VIL = 0.8 V
±10
µA
IOZ
High-impedance output current
VO = 0 or 5 V
±10
µA
CI
Input capacitance
†
6
VI = 2.4 V
5
All typical values are at 25°C and with a 3.3-V supply.
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pF
SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
driver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time
tf
Differential output signal fall time
MIN
RL = 100 Ω,
CL = 10 pF,
pF
See Figure 2
|)‡
TYP†
MAX
1.7
2.7
ns
1.7
2.7
ns
0.8
1
ns
0.8
1
ns
300
UNIT
tsk(p)
Pulse skew (|tpHL − tpLH
tsk(o)
Channel-to-channel output skew§
150
ten
Enable time
4.3
10
ns
tdis
Disable time
3.1
10
ns
See Figure 4
ps
ps
†
All typical values are at 25°C and with a 3.3-V.
‡t
sk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§t
sk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶t
sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
3.7
4.5
ns
3.7
4.5
ns
UNIT
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tsk(p)
Pulse skew (|tpHL − tpLH|)‡
tr
Output signal rise time
0.7
1.5
ns
tf
Output signal fall time
0.9
1.5
ns
tPZH
Propagation delay time, high-level-to-high-impedance output
2.5
ns
tPZL
Propagation delay time, low-level-to-low-impedance output
2.5
ns
tPHZ
Propagation delay time, high-impedance-to-high-level output
7
ns
tPLZ
Propagation delay time, low-impedance-to-high-level output
4
ns
CL = 10 pF, See Figure 6
See Figure 7
0.3
ns
†
All typical values are at 25°C and with a 3.3-V.
tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output.
§t
sk(o) is the magnitude of the time difference between the outputs of a single device with all of their inputs connected together.
¶t
sk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
‡
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
driver
IOY
Driver Enable
Y
II
A
IOZ
VOD
V
VOY
Z
VI
OY
)V
OZ
2
VOC
VOZ
Figure 1. Driver Voltage and Current Definitions
Driver Enable
Y
VOD
Input
100 Ω
±1%
Z
CL = 10 pF
(2 Places)
2V
1.4 V
0.8 V
Input
tPHL
tPLH
100%
80%
Output
VOD(H)
0V
VOD(L)
20%
0%
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
8
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HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
driver (continued)
49.9 Ω, ±1% (2 Places)
Driver Enable
3V
Y
0V
Input
Z
VOC
VOC(PP)
CL = 10 pF
(2 Places)
VOC(SS)
VOC
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP)
is made on test equipment with a −3 dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
49.9 Ω, ±1% (2 Places)
Y
0.8 V or 2 V
Z
DE
1.2 V
CL = 10 pF
(2 Places)
VOY
VOZ
2V
1.4 V
0.8 V
DE
VOY or VOZ
ten
D at 2 V and input to DE
1.2 V
1.15 V
~1 V
D at 0.8 V and input to DE
tdis
VOZ or VOY
ten
~1.4 V
1.25 V
1.2 V
tdis
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T.
Figure 4. Enable and Disable Time Circuit and Definitions
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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
receiver
A
V
IA
)V
IB
R
VID
2
VIA
B
VIC
VO
VIB
Figure 5. Receiver Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
(V)
10
RESULTING DIFFERENTIAL
INPUT VOLTAGE
(mV)
RESULTING COMMONMODE INPUT VOLTAGE
(V)
VID
VIC
VIA
VIB
1.25
1.15
100
1.2
1.15
1.25
−100
1.2
2.4
2.3
100
2.35
2.3
2.4
−100
2.35
0.1
0
100
0.05
0
0.1
−100
0.05
1.5
0.9
600
1.2
0.9
1.5
−600
1.2
2.4
1.8
600
2.1
1.8
2.4
−600
2.1
0.6
0
600
0.3
0
0.6
−600
0.3
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SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
−0.4 V
tPHL
VO
tPLH
VOH
2.4 V
1.4 V
0.4 V
VOL
tf
tr
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 6. Timing Test Circuit and Waveforms
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SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
receiver (continued)
1.2 V
B
500 Ω
A
Inputs
RE
CL
10 pF
+
−
VO
VTEST
NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
2.5 V
VTEST
A
1V
2V
1.4 V
RE
0.8 V
tPZL
tPZL
tPLZ
2.5 V
1.4 V
R
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
RE
1.4 V
0.8 V
tPZH
R
tPZH
tPHZ
VOH
VOH −0.5 V
1.4 V
0V
Figure 7. Enable/Disable Time Test Circuit and Waveforms
12
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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
DISABLED DRIVER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
Disabled Driver Output Current − mA
40
VCC = 3.3 V
TA = 25°C
DE = 0 V
30
VOZ = 0 V
20
VOZ = 1.2 V
10
VOZ = VOY
0
−10
VOZ = 2.4 V
−20
−30
0
0.5
1
1.5
2
VO − Output Voltage − V
2.5
3
Figure 8
DRIVER
DRIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
3.5
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
4
3
2
1
0
0
2
4
6
IOL − Low-Level Output Current − mA
VCC = 3.3 V
TA = 25°C
3
2.5
2
1.5
1
0.5
0
−3
−4
−2
−1
0
IOH − High-Level Output Current − mA
Figure 9
Figure 10
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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
RECEIVER
RECEIVER
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Votlage − V
5
4
3
2
1
10
20
30
40
50
IOL − Low-Level Output Current − mA
2
1
0
−80
0
0
3
60
−60
−40
−20
IOH − High-Level Output Current − mA
Figure 12
Figure 11
DRIVER
DRIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2
t PLH − Low-To-High Propagation Delay Time − ns
t PHL − High-To-Low Propagation Delay Time − ns
2.5
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
−50
−30
−10
50
30
70
TA − Free-Air Temperature − °C
10
90
2.5
2
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
1.5
−50
−30
Figure 13
14
0
−10
50
10
30
70
TA − Free-Air Temperature − °C
Figure 14
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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
TYPICAL CHARACTERISTICS
t PLH − High-To-Low Level Propagation Dealy Time − ns
RECEIVER
HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
4.5
VCC = 3.3 V
4
VCC = 3 V
3.5
VCC = 3.6 V
3
2.5
−50
−30
−10
50
10
30
70
TA − Free−Air Temperature − °C
90
Figure 15
t PLH − Low-To-High Level Propagation Delay Time − ns
RECEIVER
LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME
vs
FREE−AIR TEMPERATURE
4.5
VCC = 3 V
4
VCC = 3.3 V
3.5
VCC = 3.6 V
3
2.5
−50
−30
−10
50
10
30
70
TA − Free-Air Temperature − °C
90
Figure 16
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SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground
differences are less than 1 V with a low common−mode output and balanced interface for very low noise emissions.
Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the
power and dual supply requirements.
Transmission Distance − m
1000
30% Jitter
100
5% Jitter
10
1
24 AWG UTP 96 Ω (PVC Dielectric)
0.1
100k
1M
10M
Data Rate − Hz
Figure 17. Data Transmission Distance Versus Rate
16
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100M
SN65LVDS179-Q1, SN65LVDS180-Q1, SN65LVDS050-Q1, SN65LVDS051-Q1
HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS
SGLS204A − SEPTEMBER 2003 − REVISED APRIL 2008
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between −100 mV and
100 mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how
it handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 18. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt
100 Ω Typ
Y
B
VIT ≈ 2.3 V
Figure 18. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
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PACKAGE OPTION ADDENDUM
www.ti.com
26-Mar-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS051DRG4Q1
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS051DRQ1
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS051PWRG4Q1
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TBD
Lead/Ball Finish
MSL Peak Temp (3)
SN65LVDS051PWRQ1
ACTIVE
TSSOP
PW
16
2000
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDS180DRG4Q1
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS180DRQ1
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS180PWRG4Q1
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS180PWRQ1
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS051-Q1, SN65LVDS180-Q1 :
• Catalog: SN65LVDS051, SN65LVDS180
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
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