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PCM3500
®
PCM
350
0
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information, visit www.burr-brown.com
Low Voltage, Low Power, 16-Bit, Mono
VOICE/MODEM CODEC
TM
FEATURES
● POWER SUPPLY: Single +2.7V to +3.6V
● SMALL PACKAGE: SSOP-24
● 16-BIT DELTA-SIGMA DAC AND ADC
● DESIGNED FOR MODEM ANALOG FRONT END:
Supports up to 56kbps Operation
● ANALOG PERFORMANCE:
Sampling Frequency: 7.2kHz to 26kHz
Dynamic Range: 88dB (typ) at fS = 8kHz, fIN = 1kHz
● SYSTEM CLOCK: 512fS
● MASTER OR SLAVE OPERATION
● ON-CHIP CRYSTAL OSCILLATOR CIRCUIT
● ADC-TO-DAC LOOP-BACK MODE
● TIME SLOT MODE SUPPORTS UP TO
FOUR CODECs ON A SINGLE SERIAL
INTERFACE
● POWER-DOWN MODE: 60µA (typ)
APPLICATIONS
● SOFTWARE MODEMS FOR:
Personal Digital Assistant
Notebook and Hand-Held PCs
Set-Top Box
Digital Television
Embedded Systems
● PORTABLE VOICE RECORDER/PLAYER
● SPEECH RECOGNITION/SYNTHESIS
● TELECONFERENCING PRODUCTS
DESCRIPTION
digital-to-analog and analog-to-digital converters, input anti-aliasing filter, digital high-pass filter for DC
blocking, and an output low-pass filter. The synchronous serial interface provides for a simple, or glue-free
interface to popular DSP and RISC processors. The
serial interface also supports Time Division Multiplexing (TDM), allowing up to four CODECs to share a
single 4-wire serial bus.
The PCM3500 integrates all of the functions needed for
a modem or voice CODEC, including delta-sigma
∆Σ
Modulator
(ADC)
VIN
AAF
AGND
Decimation
Digital Filter
HPF
FS
Loop
VREF1
VCOM
Reference
VREF2
VOUT
∆Σ
Modulator
Multi-Level
DAC
SMF
AGND
AGND
DGND
DOUT
FSO
Clock
Gen/
OSC
Mode Control
VDD PDWN
DIN
Interpolation
Digital Filter
Power
VCC
BCK
Serial I/O Interface
The PCM3500 is a low cost, 16-bit CODEC designed
for modem Analog Front End (AFE) and speech processing applications. The PCM3500’s low power operation from +2.7V to +3.6V power supplies, along
with an integrated power-down mode, make it ideal for
portable applications.
LOOP
HPFD
M/S
TSC
XTO
www.BDTIC.com/TI
SCKIO
XTI
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS117
PDS-1524B
1
Printed in U.S.A. February, 2000
PCM3500
®
SPECIFICATIONS
All specifications at +25°C, VDD = VCC = 3.3V, fS = 8kHz, and nominal system clock (XTI) = 512fS, unless otherwise noted. Measurement band is 100Hz to 0.425fS.
PCM3500E
PARAMETER
CONDITIONS
MIN
RESOLUTION
DATA FORMAT
Serial Data Interface Format
Serial Data Bit Length
Serial Data Format
Sampling Frequency, fS
System Clock Frequency, 512fS
ADC and DAC
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level: VIH(1)
VIL(1)
Input Logic Current: IIN(2)
IIN(3)
Output Logic Level: VOH(4)
VOL(4)
TYP
MAX
UNITS
16
Bits
DSP Format
16
Bits
MSB-First, Binary Two’s Complement
7.2
8
26
3.686
4.096
13.312
kHz
MHz
CMOS
0.7 • VDD
0.3 • VDD
±1
100
IOUT = –1mA
I OUT = +1mA
VDD – 0.3
0.3
VDC
VDC
µA
µA
VDC
VDC
ADC CHARACTERISTICS
DC ACCURACY
Input Voltage
Gain Error
Offset Error
Input Resistance
0.6 VCC
±2
±2
50
High-Pass Filter Disabled
AC ACCURACY
THD+N
Dynamic Range
Signal-to-Noise Ratio
Crosstalk
Passband Ripple (internal HPF enabled)
Passband Ripple (internal HPF disabled)
Roll-Off at 0.00002fS
Roll-Off at 0.56fS
Stopband Rejection
Group Delay
fIN = 1kHz, VIN = –0.5dB
Without A-Weighting
Without A-Weighting
DAC Channel Idle, 0dB Input
0.0002fS to 0.425fS
0fS to 0.425fS
High-Pass Filter Enabled
High-Pass Filter Enabled
0.58fS to fS
82
82
80
–85
88
88
85
±0.05
±0.05
–3
–30
–65
18/fS
±5
–80
4m
Vp-p
% of FSR
% of FSR
kΩ
dB
dB
dB
dB
dB
dB
dB
dB
dB
sec
DAC CHARACTERISTICS
DC ACCURACY
Output Voltage
Gain Error
Offset Error
Load Resistance
0.6 VCC
±1
±1
High Pass Filter Disabled
±5
10
AC ACCURACY
THD+N
Dynamic Range
Signal-to-Noise Ratio
Crosstalk
Passband Ripple
Group Delay
fIN = 1kHz, VOUT = 0dB
Without A-Weighted
Without A-Weighted
ADC Channel Idle, 0dB Input
0fS to 0.425fS
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current, ICC + IDD
Total Supply Current in Power-Down Mode
Total Power Dissipation
VCC
VCC, VDD
VCC = 3.3V
= VDD = 3.3V, XTI Stopped
VCC = VDD = 3.3V
TEMPERATURE RANGE
Operating
Storage
Thermal Resistance, ΘJA
84
84
84
2.7
–90
92
92
92
±0.4
12/fS
–82
3.3
9
60
30
3.6
12
–25
–55
4m
40
+85
+125
100
Vp-p
% of FSR
% of FSR
kΩ
dB
dB
dB
dB
dB
sec
VDC
mA
µA
mW
°C
°C
°C/W
NOTES: (1) Pins 6, 7, 8, 9, 10, 15, 17, 18, 19, 20 (M/S, TSC, BCK, FS, DIN, SCKIO, XTI, HPFD, LOOP, PDWN). (2) Pins 8, 9, 10, 15, 17 (BCK, FS, DIN, SCKIO
(Schmitt-Trigger input) XTI. (3) Pins 6, 7, 18, 19, 20 (M/S, TSC, HPFD, LOOP, PDWN; Schmitt-Trigger input with internal pull-down). (4) Pins 8, 9, 11, 12, 15,
16 (BCK, FS, DOUT, FSO, SCKIO, XTO).
®
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PCM3500
2
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Supply Voltage, +VDD, +VCC ............................................................. +6.5V
Supply Voltage Differences ............................................................... ±0.1V
GND Voltage Differences .................................................................. ±0.1V
Digital Input Voltage ................................................... –0.3V to VDD + 0.3V
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Input Current (any pins except supply) ........................................... ±10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... –25°C to +85°C
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
Storage Temperature ...................................................... –55°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 5s) .................................................. +260°C
(reflow, 10s) ................................................................................ +235°C
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM3500E
"
24-Lead SSOP
"
338
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
–25°C to +85°C
"
PCM3500E
"
PCM3500E
PCM3500E/2K
Rails
Tape and Reel
NOTES: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2,000 pieces
of “PCM3500E/2K” will get a single 2000-piece Tape and Reel.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no
responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN
product for use in life support devices and/or systems.
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3
PCM3500
®
PIN CONFIGURATION
Top View
SSOP
PCM3500
1
VCOM
VCC 24
2
VREF1
AGND 23
3
VREF2
VOUT 22
4
VIN
AGND 21
5
AGND
PDWN 20
6
M/S
LOOP 19
7
TSC
HPFD 18
8
BCK
XTI 17
9
FS
10
DIN
SCKIO 15
11
DOUT
DGND 14
12
FSO
XTO 16
VDD 13
PIN ASSIGNMENTS
PIN
NAME
I/O
1
VCOM
OUT
DESCRIPTION
2
VREF1
—
Decouple Pin for Reference Voltage 1 (0.99VCC). This pin should be connected to ground through a capacitor.
3
VREF2
—
Decouple Pin for Reference Voltage 2 (0.2VCC). This pin should be connected to ground through a capacitor.
4
VIN
IN
Analog Input for the ADC.
5
AGND
—
Analog Ground for the ADC Input Signal.
6
M/S
IN
Master/Slave Select. This pin is used to determine the operating mode for the serial interface. A logic ‘0’ on this pin selects the Slave
Mode. A logic ‘1’ on this pin selects the Master Mode.(2)
7
TSC
IN
Time Slot Mode Control. This pin is used to select the time slot operating mode. A logic ‘0’ on this pin disables Time Slot Mode. A
logic ‘1’ on this pin enables Time Slot Mode.(2)
8
BCK
I/O
Bit Clock. This pin serves as the bit (or shift) clock for the serial interface. This pin is an input in Slave Mode and an output in Master
Mode.(1)
9
FS
I/O
Frame Sync. This pin serves as the frame synchronization clock for the serial interface. This pin is an input in Slave Mode and an
output in Master Mode.(1)
Serial Data Input. This pin is used to write 16-bit data to the DAC.(1)
Common-Mode Voltage (0.5VCC). This pin should be connected to ground through a capacitor.
10
DIN
IN
11
DOUT
OUT
Serial Data Output. The ADC outputs 16-bit data on this pin.(3)
12
FSO
OUT
Frame Sync Output. Active only when Time Slot Mode is enabled. This pin is set to a high impedance state when Time Slot mode
is disabled (TSC = 0).
13
VDD
—
Digital Power Supply. Used to power the digital section of the ADC and DAC, as well as the serial interface and mode control logic.
This pin is not internally connected to VCC.
14
DGND
—
Digital Ground. Internally connected through the substrate to analog ground.
15
SCKIO
I/O
System Clock Input/Output. This pin is a system clock output when using the crystal oscillator or XTI as the system clock input; when
XTI is connected to ground, this pin is a system clock input.(1)
16
XTO
OUT
17
XTI
IN
Crystal Oscillator Input or an External System Clock Input.
18
HPFD
IN
High-Pass Filter Disable. When this pin is set to a logic ‘1’, the HPF function in the ADC is disabled.(2)
Crystal Oscillator Output.
19
LOOP
IN
ADC-to-DAC Loop-Back Control. When this pin is set to logic ‘1’, the ADC data is fed to the DAC input.(2)
20
PDWN
IN
Power Down and Reset Control. When this pin is logic ‘0’, Power-Down Mode is enabled. The PCM3500 is reset on the rising edge
of this signal.(2)
21
AGND
—
Analog Ground for the DAC Output Signal.
22
VOUT
OUT
23
AGND
—
Analog Ground. This is the ground for the internal analog circuitry.
24
VCC
—
Analog Power Supply. Used to power the analog circuitry of the ADC and DAC.
Analog Output from the DAC Output Filter.
NOTES: (1) Schmitt-Trigger input. (2) Schmitt-Trigger input with an internal pull-down resistor. (3) Tri-state output in Time Slot Mode.
®
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PCM3500
4
TYPICAL PERFORMANCE CURVES
DAC SECTION
DIGITAL FILTER
INTERPOLATION FILTER
PASSBAND RIPPLE CHARACTERISTICS
INTERPOLATION FILTER FREQUENCY RESPONSE
0
0.2
–10
0.0
–30
Amplitude (dB)
Amplitude (dB)
–20
–40
–50
–60
–70
–80
–0.2
–0.4
–0.6
–0.8
–90
–100
–1.0
1
0
4
2
3
Normalized Frequency (• fS)
0
0.1
0.2
0.3
0.4
0.5
Normalized Frequency (• fS Hz)
ANALOG FILTER
OUTPUT FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
0
0
–10
–1
–20
–2
–30
–3
–40
–4
Amplitude (dB)
Amplitude (dB)
OUTPUT FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
–50
–60
–70
–80
–90
–100
100
–5
–6
–7
–8
–9
–10
1k
10k
100k
1M
10M
1
Frequency (Hz)
10
100
1k
10k
100k
Frequency (Hz)
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5
PCM3500
®
TYPICAL PERFORMANCE CURVES
(Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
DAC SECTION
DAC OUTPUT SPECTRA
DAC OUTPUT SPECTRUM (–60dB, N = 8192)
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
DAC OUTPUT SPECTRUM (–0dB, N = 8192)
0
–60
–80
–60
–80
–100
–100
–120
–120
–140
–140
0
1
2
3
4
0
1
2
3
Frequency (kHz)
Frequency (kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs SIGNAL NOISE
DAC OUT-OF-BAND NOISE SPECTRUM
(BPZ, N = 2048)
0
4
0
–20
Amplitude (dB)
THD+N (dB)
–20
–40
–60
–60
–80
–100
THD+N fluctuates with signal level
as harmonics are limited to second
and third components.
–80
–40
–120
–140
–100
–96
–84
–72
–60
–48
–36
–24
–12
0
0
®
8
16
24
32
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PCM3500
40
Frequency (kHz)
Signal Level (dB)
6
48
56
64
TYPICAL PERFORMANCE CURVES
(Cont.)
DAC SECTION
DAC CHARACTERISTICS vs TEMPERATURE, SUPPLY, AND SAMPLING FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
(TA = –25°C to +85°C)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
(TA = –25°C to +85°C)
96
Dynamic Range and SNR (dB)
THD+N at –0dB (dB)
–88
–90
–92
–94
–96
94
SNR
92
Dynamic Range
90
88
–50
–25
0
25
50
Temperature (°C)
75
100
–50
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
(VCC = VDD = +2.7V to +3.6V)
0
25
50
Temperature (°C)
100
Dynamic Range and SNR (dB)
96
–90
–92
–94
–96
94
Dynamic Range
92
SNR
90
88
2.4
2.7
3.0
3.3
Supply Voltage (V)
3.6
3.9
2.4
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
(fS = 8kHz to 26kHz)
2.7
3.0
3.3
Supply Voltage (V)
3.6
3.9
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SAMPLING FREQUENCY
(fS = 8kHz to 26kHz)
–88
96
BW = 3.4kHz
Dynamic Range and SNR (dB)
BW = 3.4kHz
THD+N at –0dB (dB)
75
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SUPPLY VOLTAGE
(VCC = VDD = +2.7V to +3.6V)
–88
THD+N at –0dB (dB)
–25
–90
–92
–94
–96
SNR
94
92
Dynamic Range
90
88
0
8
16
24
32
0
8
16
fS (kHz)
24
32
fS (kHz)
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7
PCM3500
®
TYPICAL PERFORMANCE CURVES
ADC SECTION
DIGITAL FILTER
DECIMATION FILTER
STOPBAND ATTENUATION CHARACTERISTICS
0
0
–20
–10
–40
–20
–60
–30
Amplitude (dB)
Amplitude (dB)
DECIMATION FILTER FREQUENCY RESPONSE
–80
–100
–120
–140
–40
–50
–60
–70
–80
–160
–180
–90
–200
–100
0
8
16
24
0
32
0.2
0.4
0.6
0.8
Normalized Frequency (• fS Hz)
Normalized Frequency (• fS Hz)
DECIMATION FILTER
PASSBAND RIPPLE CHARACTERISTICS
DECIMATION FILTER TRANSITION
BAND CHARACTERISTICS
1.0
0
0.2
–1
–2
Amplitude (dB)
Amplitude (dB)
0.0
–0.2
–0.4
–0.6
–4.13dB at 0.5 • fS
–3
–4
–5
–6
–7
–8
–0.8
–9
–10
–1.0
0.1
0.2
0.3
0.4
0.45 0.46 0.47 0.48 0.49 0.50 0.51 0.52 0.53 0.54 0.55
0.5
Normalized Frequency (• fS Hz)
Normalized Frequency (• fS Hz)
HIGH-PASS FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
HIGH-PASS FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
0
0.0
–10
–0.1
–20
–0.2
–30
–0.3
Amplitude (dB)
Amplitude (dB)
0
–40
–50
–60
–70
–0.4
–0.5
–0.6
–0.7
–80
–0.8
–90
–0.9
–100
–10
0
0.1
0.2
0.3
0.4
0.5
0
Normalized Frequency (• fS /1000 Hz)
®
1
2
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PCM3500
3
Normalized Frequency (• fS /1000 Hz)
8
4
TYPICAL PERFORMANCE CURVES
(Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
ADC SECTION
ANALOG FILTER
ANTI-ALIASING FILTER
PASSBAND CHARACTERISTICS
0
0
–5
–0.1
–10
–0.2
–15
–0.3
Amplitude (dB)
Amplitude (dB)
ANTI-ALIASING FILTER
STOPBAND CHARACTERISTICS
–20
–25
–30
–35
–0.4
–0.5
–0.6
–0.7
–40
–0.8
–45
–0.9
–50
100
–1.0
1k
10k
100k
1M
10M
1
10
100
Frequency (Hz)
1k
10k
100k
Frequency (Hz)
ADC OUTPUT SPECTRA
ADC OUTPUT SPECTRUM (–60dB, N = 8192)
–20
–20
–40
–40
Amplitude (dB)
0
–60
–80
–60
–80
–100
–100
–120
–120
–140
–140
0
1
2
3
0
4
1
2
3
4
Frequency (kHz)
Frequency (kHz)
TOTAL HARMONIC DISTORTION + NOISE
vs SIGNAL NOISE
0
–20
THD+N (dB)
Amplitude (dB)
ADC OUTPUT SPECTRUM (–0.5dB, N = 8192)
0
–40
–60
THD+N fluctuates with signal level
as harmonics are limited to second
and third components.
–80
–100
–96
–84
–72
–60
–48
–36
–24
–12
0
Signal Level (dB)
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9
PCM3500
®
TYPICAL PERFORMANCE CURVES
(Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
ADC SECTION
ADC CHARACTERISTICS vs TEMPERATURE, SUPPLY AND SAMPLING FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
(TA = –25°C to +85°C)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs TEMPERATURE
(TA = –25°C to +85°C)
92
Dynamic Range and SNR (dB)
THD+N at –0.5dB (dB)
–84
–86
–88
–90
–92
90
SNR
88
Dynamic Range
86
84
–50
–25
0
25
50
Temperature (°C)
75
100
–50
TOTAL HARMONIC DISTORTION + NOISE
vs SUPPLY VOLTAGE
(VCC = VDD = +2.7V to +3.6V)
25
50
Temperature (°C)
75
100
92
Dynamic Range and SNR (dB)
THD+N at –0.5dB (dB)
0
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SUPPLY VOLTAGE
(VCC = VDD = +2.7V to +3.6V)
–84
–86
–88
–90
–92
Dynamic Range
90
SNR
88
86
84
2.4
2.7
3.0
3.3
3.6
3.9
2.4
2.7
3.0
3.3
3.6
Supply Voltage (V)
Supply Voltage (V)
TOTAL HARMONIC DISTORTION + NOISE
vs SAMPLING FREQUENCY
(fS = 8kHz to 26kHz)
DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO
vs SAMPLING FREQUENCY
(fS = 8kHz to 26kHz)
–84
3.9
96
BW = 3.4kHz
BW = 3.4kHz
Dynamic Range and SNR (dB)
THD+N at –0.5dB (dB)
–25
–86
–88
–90
–92
SNR
94
92
Dynamic Range
90
88
0
8
16
24
32
0
fS (kHz)
®
8
16
fS (kHz)
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PCM3500
10
24
32
TYPICAL PERFORMANCE CURVES
(Cont.)
TA = +25°C, VCC = VDD = +3.3V, fS = 8kHz, and fSIGNAL = 1kHz, unless otherwise specified.
SUPPLY CURRENT vs SUPPLY VOLTAGE AND SAMPLING FREQUENCY
SUPPLY CURRENT vs SUPPLY VOLTAGE
12
10
10
ICC, IDD and ICC + IDD (mA)
ICC, IDD and ICC + IDD (mA)
SUPPLY CURRENT vs SUPPLY VOLTAGE
12
ICC + IDD
8
ICC
6
4
IDD
2
ICC + IDD
8
ICC
6
4
IDD
2
ICC + IDD at Power Down
ICC + IDD at Power Down
0
0
2.4
2.7
3.0
3.3
Supply Voltage (V)
3.6
3.9
2.4
2.7
3.0
3.3
Supply Voltage (V)
www.BDTIC.com/TI
11
PCM3500
3.6
3.9
®
SYSTEM CLOCK AND RESET/
POWER DOWN
SAMPLING FREQUENCY (kHz)
SYSTEM CLOCK FREQUENCY (MHz)
8
11.025
16
22.05
24
4.096
5.6448
8.192
11.2896
12.288
SYSTEM CLOCK INPUT AND OUTPUT
The PCM3500 requires a system clock for operating the
digital filters and delta-sigma data converters.
TABLE I. System Clock Frequencies for Common Sampling Frequencies.
The system clock may be supplied from an external master
clock or generated using the on-chip crystal oscillator circuit. Figure 1 shows the required connections for external
and crystal clock operation. The system clock must operate
at 512 times the sampling frequency, fS, with sampling
frequencies from 7.2kHz to 26kHz. This gives an effective
system clock frequency range of 3.6864MHz to 13.312MHz.
For either case, XTO (pin 16) should be left open. The system
clock source should be free of noise and exhibit low phase
jitter in order to obtain optimal dynamic performance from
the PCM3500. Figure 2 shows the system clock timing
requirements associated with an external master clock.
Table I shows system clock frequencies for common sampling frequencies.
For crystal oscillator operation, a crystal is connected between XTI (pin 17) and XTO (pin 16), along with the
necessary load capacitors (10pF to 33pF per pin, as shown
in Figure 1). A fundamental-mode, parallel resonant crystal
is required.
For external clock operation, XTI (pin 17) or SCKIO (pin 15)
is driven by a master clock source. If SCKIO is used as the
system clock input, then XTI must be connected to ground.
SCKIO
SCKIO
External
Clock
XTI
External
Clock
SCKIO
C1
XTI
Crystal
XTI
R
R
R
C2
XTO
XTO
XTO
C1, C2 = 10pF to 33pF
PCM3500
PCM3500
EXTERNAL CLOCK INPUT-SCKIO
(XTO must be open)
EXTERNAL CLOCK INPUT-XTI
(XTO must be open)
PCM3500
CRYSTAL RESONATOR
CONNECTION
FIGURE 1. System Clock Generation.
tCLKIH
XTI
or
SCKIO
"H"
0.7VDD
0.3VDD
"L"
1/512fS
tCLKIL
System Clock Pulse Width HIGH tCLKIH
20ns (min)
System Clock Pulse Width LOW
20ns (min)
www.BDTIC.com/TI
FIGURE 2. External System Clock Timing Requirements.
®
tCLKIL
PCM3500
12
PDWN causes the reset initialization sequence to start.
During the initialization sequence, the DAC output is forced
to AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 4 and 5 for
external reset and post-reset delay timing.
Reset and Power Down
The PCM3500 supports power-on reset, external reset, and
power-down operations. Power-on reset is performed by
internal circuitry automatically at power up, while the external reset is initiated using the PDWN input (pin 20).
Power-on reset occurs when power and system clock are
initially applied to the PCM3500. The internal reset circuitry requires that the system clock be active at power up,
with at least three system clock cycles occurring prior to
VDD = 2.2V. When VDD exceeds 2.2V, the power-on reset
comparator enables the initialization sequence, which requires 1024 system clock periods for completion. During
the initialization sequence, the DAC output is forced to
AGND, and the ADC output is forced to a high impedance
state. After the initialization sequence has completed, the
DAC and ADC outputs experience a delay before they
output a valid signal or data. Refer to Figures 3 and 5 for
power-on reset and post-reset delay timing.
External reset is performed by first setting PDWN = ‘0’ and
then setting PDWN = ‘1’. The LOW to HIGH transition on
VDD
Power-down mode is enabled by setting PDWN = ‘0’.
During power-down mode, minimum current is drawn when
the system clock is removed, resulting in 60µA (typical)
power supply current. The PDWN input includes an internal
pull-down resistor, which places the PCM3500 in powerdown mode at power-up if the PDWN pin is left unconnected. Ideally, the PDWN input should be driven by active
logic in order to control reset and power-down operation. If
the PDWN pin is to be unused in the system application, it
should be connected to VDD to enable normal operation. By
setting PDWN = ‘1’ when exiting power-down mode, the
PCM3500 will initiate an external reset as described earlier
in this section.
2.4V
2.2V
2.0V
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
FIGURE 3. Power-On Reset Timing.
PWDN = LOW Pulse Width
tRST = 40ns minimum
PDWN
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
FIGURE 4. External Reset Timing.
Reset Removal or Power Down OFF
Internal Reset
or Power Down
DAC VOUT
Ready/Operation
Reset
Power Down
tDACDLY1 (2048/fS)
VCOM
GND
(0.5VCC)
tADCDLY1 (2304/fS)
ADC DOUT
High Impedance
(1)
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR with 200ms time constant) appears initially.
www.BDTIC.com/TI
FIGURE 5. DAC and ADC Output for Reset and Power Down.
13
PCM3500
®
SERIAL INTERFACE
anteed in Master Mode). Data for DIN is clocked into the
serial interface on the rising edge of BCK, while data for
DOUT is clocked out of the serial interface on the falling
edge of BCK.
The serial interface of the PCM3500 is a 4-wire synchronous
serial port. It includes FS (pin 9), BCK (pin 8), DIN (pin 10)
and DOUT (pin 11). FS is the frame synchronization clock,
BCK is the serial bit or shift clock, DIN is the serial data input
for the DAC, and DOUT is the serial data output for the ADC.
Figure 6 shows the serial interface format for the PCM3500.
The serial data for DIN and DOUT must be in Binary Two’s
Complement, MSB-first format. Figures 7 and 8 show the
timing specifications for the serial interface when used in
Slave and Master Modes.
The frame sync, FS, operates at the sampling frequency (fS).
The bit clock, BCK, operates at 16fS for normal operation.
DIN and DOUT also operate at the bit clock rate. Both FS
and BCK must be synchronous with the system clock (guar-
FS
BCK
DIN
15 14 13 12 11
MSB
DOUT
15 14 13 12 11
MSB
5
4
3
2
1
0 15 14 13 12 11
LSB MSB
5
4
3
2
1
0
LSB
5
4
3
2
1
0 15 14 13 12 11
LSB MSB
5
4
3
2
1
0
LSB
1/fS
16-Bit/Frame
FIGURE 6. Serial Interface Format.
tFSP
tFSW
FS
(input)
0.5VDD
tFSSU
tFSHD
tBCKP
BCK
(input)
0.5VDD
tBCKH
tBCKL
DIN
(input)
0.5VDD
tDISU
tDIHD
DOUT
(output)
0.5VDD
tCKDO
NOTES: Timing measurement reference level is (VIH/VIL)/2. RIsing and falling time is measured
from 10% to 90% of IN/OUT signal swing. Load capacitance of DOUT signal is 50pF.
SYMBOL
DESCRIPTION
MIN
tBCKP
tBCKH
tBCKL
tFSW
tFSP
tFSSU
tFSHD
tDISU
tDIHD
tCKDO
tR
tF
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
FS Pulse Width HIGH
FS Period
FS Set Up Time to BCK Rising Edge
FS Hold Time to BCK Rising Edge
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Rising Time of All Signals
Falling Time of All Signals
2400
800
800
tBCKP – 60
tBCKP
1/fS
MAX
UNITS
tBCKP + 60
ns
ns
ns
ns
80
30
30
ns
ns
ns
ns
ns
ns
ns
www.BDTIC.com/TI
FIGURE 7. Serial Interface Timing for Slave Mode.
®
60
60
60
60
0
TYP
PCM3500
14
tFSP
tFSW
FS
(output)
0.5VDD
tCKFS
tBCKP
BCK
(output)
0.5VDD
tBCKH
tBCKL
DIN
(input)
0.5VDD
tDIHD
tDISU
DOUT
(output)
0.5VDD
tCKDO
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FS, BCK signal is 50pF.
SYMBOL
DESCRIPTION
MIN
tBCKP
tBCKH
tBCKL
tCKFS
tFSW
tFSP
tDISU
tDIHD
tCKDO
tR
tF
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
Delay Time BCK Falling Edge to FS
FS Pulse Width HIGH
FS Period
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Rising Time of All Signals
Falling Time of All Signals
2400
1200
1200
– 40
tBCKP – 60
TYP
tBCKP
1/fS
60
60
0
MAX
UNITS
16000
8000
8000
40
tBCKP + 60
ns
ns
ns
ns
ns
80
30
30
ns
ns
ns
ns
ns
FIGURE 8. Serial Interface Timing for Master Mode.
System
Clock
System
Clock
PCM3500
XTI
XTI
FS
FS
BCK
Controller
PCM3500
DIN
DOUT
BCK
Controller
M/S
GND
TSC
GND
DIN
DOUT
Slave Mode
M/S
VDD
TSC
GND
Master Mode
FIGURE 9. Slave and Master Mode Connections.
MASTER/SLAVE OPERATION
Slave Mode Operation
The serial interface supports both Slave and Master Mode
operation. The mode is selected by the M/S input (pin 6).
Table II shows mode and pin settings corresponding to the
M/S input selection. Figure 9 shows connections for Slave
and Master mode operation.
In Slave Mode, the FS and BCK pins are inputs to the
PCM3500. Both FS and BCK should be derived from the
system clock signal (XTI or SCKIO) to ensure proper
synchronization. Slave Mode is best suited for applications
where the DSP or controller is capable of generating the FS,
BCK, and system clocks using an on-chip serial port and/or
timing generator.
M/S (PIN 6)
SERIAL
INTERFACE
MODE
FS (PIN)
BCK (PIN 8)
0
1
Slave
Master
Input
Output
Input
Output
Master Mode Operation
In Master Mode operation, both FS and BCK are clock
outputs generated by the PCM3500 from the system clock
input (XTI, SCKIO, or a crystal). In Master Mode, the timing
and phase relationships between system clock, FS, and BCK
are managed internally to provide optimal synchronization.
www.BDTIC.com/TI
TABLE II. Master/Slave Mode Selection.
15
PCM3500
®
interface bus. This is useful for system applications that
require multiple modem or voice channels. Figure 11 shows
examples of Time Slot Mode connections.
SYNCHRONIZATION REQUIREMENTS
The PCM3500 requires that FS and BCK be synchronous
with the system clock. Internal circuitry is included to detect
a loss of synchronization between FS and the system clock
input. If the phase relationship between FS and the system
clock varies more than ± 1.5 BCK periods, the PCM3500
will detect a loss of synchronization. Upon detection, the
DAC output is forced to 0.5VCC and the DOUT pin is forced
to a high impedance state. This occurs within one sampling
clock (FS) period of initial detection. Figure 10 shows the
loss of synchronization operation and the DAC and ADC
output delays associated with it.
Time Slot Mode defines a 64-bit long frame, composed of
four time slots. Each slot is 16 bits long and corresponds to
one of four CODECs. The FS pin on the first PCM3500
(CODEC A, Slot 0) is used as the master frame sync, and
operates at the sampling frequency, fS. The bit clock, BCK,
operates at 64fS. DIN and DOUT of each CODEC also
operate at 64fS. Figure 12 shows the operation of the Time
Slot Mode.
Time Slot operation is enabled or disabled using the TSC
input (pin 7). The state of the TSC pin is updated at poweron reset, or on the rising edge of PWDN input (if using
external reset or power-down mode). A forced reset is
required when changing from Slave to Master Mode, or visa
versa, in real time.
TIME SLOT OPERATION
The PCM3500 serial interface supports Time Division
Multiplexing (TDM) using the Time Slot Mode. Up to four
PCM3500s may be connected on the same 4-wire serial
Synchronization
Lost
State of
Synchronization
Synchronous
Resynchronization
Asynchronous
Synchronous
within
1/fS
Undefined Data
DAC VOUT
Normal
tDACDLY2 (32/fS)
VCOM
(0.5 VCC)
Normal
tADCDLY2 (32/fS)
Undefined Data
ADC DOUT
VCOM
(0.5 VCC)
High Impedance
Normal
Normal(1)
NOTE: (1) The HPF transient response (exponentially attenuated signal from ±0.2% DC of FSR
with 200ms time constant) appears initially.
FIGURE 10. Loss of Synchronization Operation and Timing.
PCM3500
(CODEC A, Slot 0)
SCKIO
FS
Controller
BCK
XTI
XTO
DIN
M/S
VDD
DOUT
TSC
VDD
FSO
PCM3500
(CODEC B, Slot 1)
SCKIO
FS
BCK
XTI
XTO
DIN
M/S
GND
DOUT
TSC
VDD
FSO
www.BDTIC.com/TI
To Two PCM3500s
FIGURE 11. Time Slot Mode Connections.
®
PCM3500
16
One Frame = 1/fS, 64 Bits per Frame, 16 Bits per Slot
CODEC A
CODEC B
CODEC C
CODEC D
Slot 0, 16 Bits
Slot 1, 16 Bits
Slot 2, 16 Bits
Slot 3, 16 Bits
FS
BCK
FS (A)
FSO (A)
FS (B)
FSO (B)
FS (C)
FSO (C)
FS (D)
FSO (D)
DIN
MSB
LSB
High Impedance
DOUT (A)
High Impedance
DOUT (B)
DOUT (C)
High Impedance
High Impedance
High Impedance
DOUT (D)
FIGURE 12. Time Slot Mode Operation.
www.BDTIC.com/TI
17
PCM3500
®
ate in Loop-Back Mode, allowing the host to read the ADC
data at the DOUT pin.
Table III shows the TSC pin settings and corresponding
mode selections. When Time Slot Mode is enabled, FSO
(pin 12) is used as a frame sync output, which is connected
to the FS input of the next PCM3500 in the Time Slot
sequence. Figures 13 and 14 provide detailed timing for
Time Slot Mode operation.
LOOP (PIN 19)
LOOP-BACK MODE
0
1
Loop-Back Mode Disabled, Normal Operation
Loop-Back Mode Enabled
TABLE IV. Loop-Back Mode Selection.
TSC (PIN 7)
TIME SLOT MODE
0
1
Time Slot Mode Disabled, Normal Operation
Time Slot Operation Enable
HIGH-PASS FILTER
The PCM3500 includes a digital high-pass filter in the ADC
which may be used to remove the DC offset created by the
analog front-end (AFE) section. The high-pass filter response
is shown in Figure 15. The high-pass filter may be enabled or
disabled using the HPFD input (pin 18). Table V shows the
HPFD pin settings and corresponding mode selections.
TABLE III. Time Slot Mode Selection.
ADC-TO-DAC LOOP BACK
The PCM3500 includes a Loop-Back Mode, which directly
feeds the ADC data to the DAC input. This mode is designed
for diagnostic testing and system adjustment. Loop-Back
Mode is enabled and disabled using the LOOP input (pin
19). Table IV shows the LOOP pin settings and corresponding mode selections. The serial interface continues to oper-
HPFD (PIN 18)
HIGH-PASS FILTER MODE
0
1
High-Pass Filter On
High-Pass Filter Off
TABLE V. High-Pass Filter Mode Selection.
tFSP
tFSW
FS
(input)
0.5VDD
tFSSU
tFSHD
tBCKP
BCK
(input)
0.5VDD
tBCKL
tBCKH
DIN
(input)
0.5VDD
tDISU
tDIHD
High Impedance
High Impedance
DOUT
(output)
0.5VDD
tHZDO
tCKDO
tDOHZ
FSO
(output)
0.5VDD
tBFSO
tFSOW
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, and FSO signal is 50pF.
SYMBOL
DESCRIPTION
MIN
t BCKP
t BCKH
t BCKL
t FSW
t FSP
t FSSU
t FSHD
t DISU
t DIHD
t CKDO
t HZDO
t DOHZ
t FSOW
t BFSO
tR
tF
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
FS Pulse Width HIGH
FS Period
FS Set Up TIme to BCK Rising Edge
FS Hold TIme to BCK RIsing Edge
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Delay Time BCK Falling Edge to DOUT Active
Delay Time BCK Falling Edge to DOUT Inactive
FSO Pulse Width HIGH
Delay Time BCK Falling Edge to FSO
Rising Time of All Signals
Falling Time of All Signals
600
200
200
tBCKP – 60
TYP
tBCKP
1/fS
60
60
60
60
0
tBCKP – 60
0
UNITS
tBCKP + 60
ns
ns
ns
ns
80
20
19.5
tBCKP
tBCKP + 60
80
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
www.BDTIC.com/TI
FIGURE 13. Serial Interface Timing for Time Slot Mode Operation (Slave Mode).
®
MAX
PCM3500
18
tFSP
tFSW
FS
(output)
0.5VDD
tBCKP
tCKFS
BCK
(output)
0.5VDD
tBCKL
tBCKH
DIN
(input)
0.5VDD
tDIHD
tDISU
High Impedance
High Impedance
DOUT
(output)
0.5VDD
tHZDO
tCKDO
tDOHZ
FSO
(output)
0.5VDD
tBFSO
tFSOW
NOTES: Timing measurement reference level is (VIH/VIL)/2. Rising and falling time is measured from
10% to 90% of IN/OUT signal swing. Load capacitance of DOUT, FSO, FS, and BCK signal is 50pF.
SYMBOL
DESCRIPTION
MIN
tBCKP
tBCKH
tBCKL
tCKFS
tFSW
tFSP
tDISU
tDIHD
tCKDO
tHZDO
tDOHZ
tFSOW
tBFSO
tR
tF
BCK Period
BCK Pulse Width HIGH
BCK Pulse Width LOW
Delay Time BCK Falling Edge to FS
FS Pulse Width HIGH
FS Period
DIN Set Up Time to BCK Rising Edge
DIN Hold Time to BCK Rising Edge
Delay Time BCK Falling Edge to DOUT
Delay Time BCK Falling Edge to DOUT Active
Delay Time BCK Falling Edge to DOUT Inactive
FSO Pulse Width HIGH
Delay Time BCK Falling Edge to FSO
Rising Time of All Signals
Falling Time of All Signals
600
300
300
–40
tBCKP – 60
TYP
tBCKP
1/fS
60
60
0
tBCKP – 60
0
MAX
UNITS
4000
2000
2000
40
tBCKP + 60
ns
ns
ns
ns
ns
80
20
19.5
tBCKP
tBCKP + 60
80
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIGURE 14. Serial Interface Timing for Time Slot Mode Operation (Master Mode).
HIGH-PASS FILTER FREQUENCY RESPONSE
PASSBAND CHARACTERISTICS
0
0.0
–10
–0.1
–20
–0.2
–30
–0.3
Amplitude (dB)
Amplitude (dB)
HIGH-PASS FILTER FREQUENCY RESPONSE
STOPBAND CHARACTERISTICS
–40
–50
–60
–70
–0.4
–0.5
–0.6
–0.7
–80
–0.8
–90
–0.9
–100
–10
0
0.1
0.2
0.3
0.4
0.5
0
Normalized Frequency (• fS /1000 Hz)
1
2
3
4
Normalized Frequency (• fS /1000 Hz)
www.BDTIC.com/TI
FIGURE 15. High-Pass Filter Response.
19
PCM3500
®
APPLICATIONS INFORMATION
unbuffered on pin 1 for decoupling. A 1µF to 10µF aluminum electrolytic or tantalum capacitor is recommended for
decoupling purposes. This capacitor should be located as
close as possible to pin 1.
BASIC CIRCUIT CONNECTIONS
The basic connection diagram for the PCM3500 is shown in
Figure 16. Included are the required power supply bypass and
reference decoupling capacitors. The DAC output, VOUT, and
the ADC input, VIN, should be AC-coupled to external circuitry.
The VCOM voltage is typically equal to VCC/2, and may be
used to bias external input and output circuitry. However,
since the VCOM pin is not a buffered output, it must drive a
high impedance load to avoid excessive loading. Buffering
the VCOM pin with an external op amp configured as a
voltage follower is recommended when driving multiple bias
nodes. Figure 17 shows examples of using VCOM with
external circuitry.
Reference Pin Connections
The VCOM voltage is used internally to bias the input and
output amplifier stages of the PCM3500. It is brought out
C3 +
C4 +
C5 +
Serial
Interface
+
PCM3500
1
VCC 24
VCOM
2
VREF1
AGND 23
3
VREF2
VOUT 22
4
VIN
AGND 21
5
AGND
PDWN 20
6
M/S
LOOP 19
7
TSC
HPFD 18
8
BCK
XTI 17
9
FS
10
DIN
SCKIO 15
11
DOUT
DGND 14
12
FSO
+
+3.3V
C1
External Reset
Power-Down Control
XTO 16
External Clock System
C2
+
VDD 13
+
C6
C7
Analog Line Interface Circuit
Telecom Line
C1, C2: Power supply bypass capacitors. Parallel combination of a 1µF to 10µF aluminum electrolytic capacitor and 0.1µF ceramic capacitor.
C3, C4, C5: VREF and VCOM bypass capacitors. Use a 1µF to 10µF aluminum electrolytic capacitor.
C6, C7: Input/output AC-coupling capacitors. Use a 0.1µF to 10µF aluminum electrolytic capacitor.
FIGURE 16. Basic Connection Diagram.
(a) Biasing an External Active Filter Stage
PCM3500
VOUT
VCC
Non-Polarized
1µF
(b) Using a Buffer to Provide Bias for Multiple or
Low Input Impedance Nodes
OPA343
VCOM
+
4.7µF
Use voltage follower
to buffer VCOM
PCM3500
VCOM
+
OPA340
www.BDTIC.com/TI
FIGURE 17. Using VCOM to Bias External Circuitry.
®
4.7µF
PCM3500
20
To Bias
Nodes
VREF1 (pin 2) and VREF2 (pin 3) are reference voltages used
by the delta-sigma modulators. They are brought out strictly
for decoupling purposes. VREF1 and VREF2 are not to be
used to bias external circuits. A 1µF to 10µF aluminum
electrolytic or tantalum capacitor is recommended for
decoupling on each pin. These capacitors should be located
as close as possible to pins 2 and 3.
by a split ground plane, with the PCM3500 positioned
entirely over the analog section of the board. The AGNDs
(pins 5, 20, and 23) and DGND (pin 14) are connected
directly to the analog ground plane. The power supply pins,
VCC (pin 13) and VDD (pin 24), are routed directly to the
+2.7V to +3.6V analog power supply using wide copper
traces (100 mils or wider recommended) or a power plane.
Power supply bypass and reference decoupling capacitors
are shown located as close as possible to the PCM3500.
Power Supplies and Grounding
VCC (pin 24) and VDD (pin 13) should be connected directly
to the +2.7V to +3.6V analog power supply, as shown in
Figure 16. The AGNDs (pins 5, 21, and 23) and DGND (pin
14) should be connected directly to the analog ground.
Power supply bypass capacitors should be located as close
to the power supply pins as possible in order to ensure a low
impedance connection. A combination of a 10µF aluminum
electrolytic or tantalum capacitor in parallel with a 0.1µF
ceramic capacitor is recommended for both VCC and VDD.
The PCM3500 is oriented so that the digital pins are facing
the ground plane split. Digital connections should be made
as short and direct as possible to limit high frequency
radiation and coupling. Series resistors (from 20Ω to 100Ω)
may be put in series with the system clock, FS, BCK, and
FSO lines to reduce or eliminate overshoot on clock edges,
further reducing radiated emissions. The split ground plane
should be connected at one point by a trace, wire, or ferrite
bead. Often the board will be designed to have several
jumper points for the common ground connection, so that
the best performance can be derived through experimentation.
VDD and VCC should not be connected to separate digital and
analog power supplies. This can lead to an SCR latch-up
condition, which can cause either degraded device performance or catastrophic failures.
An alternative technique, using a single power supply or
battery, is shown in Figure 19. This technique is more
suitable for portable applications.
PCB LAYOUT GUIDELINES
The recommended PCB layout technique is shown in Figure
18. The analog and digital section of the board are separated
Digital Power
Supply
Analog Power
Supply
Common
Connection
+3.3V
VCC
Host
and
Logic
Common
Supply
+3.3V
Ferrite
Beads
VDD
VCC
PCM3500
Host
and
Logic
AGND DGND
PCM3500
AGND DGND
Digital I/Os
DIGITAL SECTION
VDD
Digital I/Os
ANALOG SECTION
DIGITAL SECTION
ANALOG SECTION
Split Grounds
Split Grounds
Analog
Ground
Digital
Ground
Analog
Ground
FIGURE 18. Recommended PCB Layout Technique.
Digital
Ground
FIGURE 19. PCB Layout Using a Single-Supply or Battery.
www.BDTIC.com/TI
21
PCM3500
®
OUTPUT FILTER CIRCUITS FOR THE DAC
noise requirements for a particular system. Generally, a 2ndorder or better low-pass circuit will be required, with the
cut-off frequency set to fS/2 or less.
The PCM3500’s DAC uses delta-sigma conversion techniques. It uses oversampling and noise shaping to improve
in-band (f = fS/2) signal-to-noise performance at the expense
of increased out-of-band noise. The DAC output must be
low-pass filtered to attenuate the out-of-band noise to a
reasonable level.
Burr-Brown Application Bulletin AB-034 provides information for designing both Multiple Feedback and SallenKey active filter circuits using software available from BurrBrown’s web site. Another excellent reference for both
passive and active filter design is the “Electronic Filter
Design Handbook, Third Edition” by Williams and Taylor,
published by McGraw-Hill.
The PCM3500 includes a low-pass filter in the on-chip
output amplifier circuit. The frequency response for this
filter is shown in Figure 20. Although this filter helps to
lower the out-of-band noise, it is not adequate for many
applications. This is especially true for applications where
the sampling frequency is below 16kHz, since the out-ofband noise above fS/2 is in the audio spectrum. An external
filter circuit, either passive or active, is required to provide
additional attenuation of the out-of-band noise. The lowpass filter order will be dependent upon the out-of-band
ON-CHIP ANALOG FRONT END FOR THE ADC
The PCM3500 A/D converter includes a fully differential
input delta-sigma modulator. In order to simplify connection
for single-ended applications, an analog front end (AFE)
circuit has been included on the PCM3500 just prior to the
modulator. The AFE circuit is shown in Figure 21.
OUTPUT FILTER
PASSBAND FREQUENCY RESPONSE
0
0
–10
–1
–20
–2
–30
–3
–40
–4
Amplitude (dB)
Amplitude (dB)
OUTPUT FILTER
STOPBAND FREQUENCY RESPONSE
–50
–60
–70
–80
–90
–5
–6
–7
–8
–9
–100
100
–10
1k
10k
100k
1M
10M
1
Frequency (Hz)
10
100
1k
Frequency (Hz)
FIGURE 20. DAC Output Amplifier Filter Response.
1.0µF
50kΩ
VIN
4
+
(+)
(–)
VCOM
1
VREF1
+
+
2
VREF2
3
Reference
+
www.BDTIC.com/TI
FIGURE 21. On-Chip AFE Circuit for the ADC.
®
Delta-Sigma
Modulator
PCM3500
22
10k
100k
The AFE circuit consists of a single-ended-to-differential
converter, with the first stage of the circuit doubling as a
low-pass, anti-alias filter. The frequency response for the
filter is shown in Figure 22. Since the delta-sigma modulator
oversamples the input at 64fS, the anti-alias filter requirements are relaxed, with only a single-pole filter being required. If an application requires further band limiting of the
input signal, a simple RC filter at the VIN input (pin 4) can
be used, as shown in Figure 23.
provide the complete modem function. Figure 24 shows a
simplified block diagram of a software modem using the
PCM3500.
The DAA provides the interface between the CODEC and
two-wire telephone line. The DAA provides numerous
functions, including two-to-four wire conversion, modemside to line-side isolation, ring detection, hook switch control, line current compensation, and overvoltage protection.
The host CPU provides the data pump and supervisory
functions for the software modem application. The host
executes modem software code, which includes the necessary routines for transmit and receive functions, error detection and correction, echo cancellation, and CODEC/DAA
control and supervision.
SOFTWARE MODEM
APPLICATIONS
The PCM3500 was designed to meet the requirements for
software-based analog modems, supporting up to 56kbps(1).
In a software modem application, the PCM3500 is paired
with a Data Access Arrangement (DAA) and a host CPU to
NOTE: (1) Data transmission is limited to 53kbps over standard telephone
lines. Actual transmission rates vary depending upon the quality of the
lines and switching equipment for a given connection.
ANTI-ALIASING FILTER
PASSBAND CHARACTERISTICS
0
0
–5
–0.1
–10
–0.2
–15
–0.3
–20
–0.4
Amplitude (dB)
Amplitude (dB)
ANTI-ALIASING FILTER
STOPBAND CHARACTERISTICS
–25
–30
–35
–40
–0.6
–0.7
–0.8
–0.9
–45
–50
100
–0.5
–1.0
1k
10k
100k
1M
1
10M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
FIGURE 22. Anti-Alias Filter Frequency Response.
Modem
Software
PCM3500
Analog
Input
R
+
VIN
C
f–3dB =
Data
Host
CPU
PCM3500
CODEC
1
2π RC
Data
Access
Arrangement
(DAA)
Tip
Ring
Controls (ring detect, off hook, etc.)
FIGURE 23. Optional External Low-Pass Filter for the
ADC.
FIGURE 24. Software Modem Block Diagram.
www.BDTIC.com/TI
23
PCM3500
®
PCM3500
TIP
P3100BA70✽
RV1
D1
CMPZDA18V
L2
LI0805D121R
L1
LI0805D121R
C14
1nF
C15
1nF
C23
0.33µF
250V
✽
R20✽
15kΩ
R3
10MΩ
D2 Bridge
R2
10MΩ
R14✽
0Ω
R18✽
12Ω
C4
27nF
R6
150kΩ
R5
150kΩ
R1✽
16.5Ω
1%
C22
22µF, 35V
Q4✽
BC817-40
Q1
MMBT6520
SOT23
R16✽
6.8MΩ
+
Q3✽
FZT605
C3
150nF
R19✽
2.4kΩ
1W, 2010
FIGURE 25. Modem AFE Application Circuit.
F1
F1250T
RING
www.BDTIC.com/TI
24
HLDR
LEDCT
HLDCAP
HKP
HKN
VDD
R4
356kΩ
R9
3.9Ω
Q2
TN2540
SOT89
C1
15nF
24
23
VSS
22
SRVCT
21
SRVAN
20
HIN
19
LINPWR
VFCAP
7
18
HLFWV
ONHKMC
8
17
LR1
TXAN
9
16
LR2
TXCT
10
15
END
C2
11
14
CEN
BIASEN
12
13
C1A
C1B
DL207
1
2
3
4
5
6
U1
C8✽
15nF
C2
150nF
C9
470pF
5
6
7
8
IL388
4
3
2
1
5
IL388
6
7
8
4
U4
U3
3
2
1
ISOLATION BARRIER
ISOLATION BARRIER
®
C10
470pF
C7
68nF
U2
24
23
22
21
20
19
18
17
16
15
14
13
R13✽
27kΩ
R7
25.5kΩ
R10
10kΩ
C5
15nF
10µF
+ C20
C17✽
4.7nF
R14
22kΩ
C18
1µF
1
22
4
U5
PCM3500
VCOM
VOUT
VIN
OH–
RINGD
+3.3V to 7V
✽ Optional components.
NOTES: All resistors are 0.1W, 5%, 0805, unless otherwise noted.
All capacitors values are 10%, unless otherwise noted.
R8
121kΩ
LEDCT
VSS
C1A
LSTAT
RNG
OFFHKL
OFFHK
RXOUT
ACREF
TXBIAS
AUDIN
AUDOUT
DM207
C2
RXCT
RXAN
ONHKML
ONHKM
HIN
SRVAN
SRVCT
C1B
VREF
11
TXMP
12
VDD
1
2
3
4
5
6
7
8
9
10
C1
15nF
Software Modem AFE Application Circuit
wide dynamic range and excellent power supply rejection
performance. The input signal is sampled at a 64x
oversampling rate, eliminating the need for a sample-andhold circuit, and simplifying anti-alias filtering requirements. The 5th-order delta-sigma noise shaper consists of
five integrators which use a switched-capacitor topology, a
comparator, and a feedback loop consisting of a one-bit
DAC. The delta-sigma modulator shapes the quantization
noise, shifting it out of the audio band in the frequency
domain. The high order of the modulator enables it to
randomize the modulator outputs, reducing idle tone levels.
Figure 25 shows an applications circuit which utilizes the
PCM3500 and the DAA2000 from Infineon Technologies
(Siemens) to implement a complete modem AFE. The
DAA2000 provides modem-side (DM207) and line-side
(DL207) interfaces, with optical isolation separating the
functions. The PCM3500 is connected to the modem-side of
the DAA2000. The PCM3500’s serial interface and hardware mode controls are connected to the host CPU.
The 64fS one-bit data stream from the modulator is converted to 1fS, 16-bit data words by the decimation filter,
which also acts as a low-pass filter to remove the shaped
quantization noise. The DC components can be removed by
a high-pass filter function contained within the decimation
filter.
THEORY OF OPERATION
ADC SECTION
The PCM3500 A/D converter consists of two reference
circuits, a mono single-to-differential converter, a fully differential 5th-order delta-sigma modulator, a decimation filter (including digital high pass), and a serial interface circuit.
The block diagram on the front page of this data sheet
illustrates the architecture of the ADC section, Figure 21
shows the single-to-differential converter, and Figure 26
illustrates the architecture of the 5th-order delta-sigma modulator and transfer functions.
DAC SECTION
The delta-sigma DAC section of PCM3500 is based on a 5level amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format. A block diagram of the 5-level delta-sigma
modulator is shown in Figure 27. This 5-level delta-sigma
modulator has the advantage of stability and clock jitter
sensitivity over the typical one-bit (2 level) delta-sigma
modulator. The combined oversampling rate of the deltasigma modulator and the internal 8x interpolation filter is
64fS for a 512fS system clock. The theoretical quantization
noise performance of the 5-level delta-sigma modulator is
shown in Figure 28.
An internal reference circuit with three external capacitors
provides all reference voltages which are required by the
ADC, which defines the full-scale range for the converter.
The internal single-to-differential voltage converter saves
the design, space and extra parts needed for external circuitry required by many delta-sigma converters. The internal
full-differential signal processing architecture provides a
Analog In
X(z) +
–
–
1st SW-CAP
Integrator
+
–
2nd SW-CAP
Integrator
3rd SW-CAP
Integrator
+
4th SW-CAP
Integrator
5th SW-CAP
Integrator
Qn(z)
+
+
+
+
+
+
+
+
Digital Out
Y(z)
H(z)
Comparator
1-Bit
DAC
Y(z) = STF(z) • X(z) + NTF(z) • Qn(z)
Signal Transfer Function
Noise Transfer Function
STF(z) = H(z) / [1 + H(z)]
NTF(z) = 1/ [1 + H(z)]
FIGURE 26. Simplified 5th-Order Delta-Sigma Modulator.
www.BDTIC.com/TI
25
PCM3500
®
+
+
+
In
8fS
18-Bit
+
+
Z–1
–
+
Z–1
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
2
1
64fS
0
FIGURE 27. 5-Level Delta-Sigma Modulator Block Digram.
Gain (–dB)
3rd-ORDER ∆Σ MODULATOR
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
5
10
15
20
25
30
Frequency (kHz)
FIGURE 28. Quantization Noise Spectrum.
®
www.BDTIC.com/TI
PCM3500
26
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
PCM3500E
ACTIVE
SSOP
DB
24
PCM3500E/2K
ACTIVE
SSOP
DB
PCM3500E/2KG4
ACTIVE
SSOP
PCM3500EG4
ACTIVE
SSOP
58
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
24
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
24
CU NIPDAU
Level-1-260C-UNLIM
58
Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
www.BDTIC.com/TI
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
PCM3500E/2K
Package Package Pins
Type Drawing
SSOP
DB
24
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2000
330.0
17.4
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.5
8.6
2.4
12.0
16.0
www.BDTIC.com/TI
Pack Materials-Page 1
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
PCM3500E/2K
SSOP
DB
24
2000
336.6
336.6
28.6
www.BDTIC.com/TI
Pack Materials-Page 2
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