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SN74LVC1G175-EP
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SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
SINGLE D-TYPE FLIP-FLOP
WITH ASYNCHRONOUS CLEAR
Check for Samples: SN74LVC1G175-EP
FEATURES
1
•
•
•
•
•
•
•
•
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-mA Max ICC
±24-mA Output Drive at 3.3 V
Ioff Supports Partial Power-Down-Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly/Test Site
One Fabrication Site
Available in Military (–55°C/125°C)
Temperature Range (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
DCK PACKAGE
(TOP VIEW)
(1)
CLK
1
6
CLR
GND
2
5
VCC
D
3
4
Q
Additional temperature ranges available - contact factory
DESCRIPTION/ORDERING INFORMATION
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is
transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
(2)
(3)
PACKAGE (2)
SOT (SC-70) – DCK
Reel of 3000
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
CLVC1G175MDCKREP
BUD
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
The actual top-side marking has one additional character that designates the assembly/test site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2010, Texas Instruments Incorporated
SN74LVC1G175-EP
SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
www.ti.com
FUNCTION TABLE
INPUTS
OUTPUT
Q
CLR
CLK
D
H
↑
L
L
H
↑
H
H
H
H or L
X
QO
L
X
X
L
LOGIC DIAGRAM (POSITIVE LOGIC)
CLR
CLK
D
6
1
3
D
4
C1
Q
R
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
6.5
V
Input voltage range
–0.5
6.5
V
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
259
°C/W
150
°C
VCC
Supply voltage range
VI
VO
(3)
Continuous current through VCC or GND
qJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
2
(4)
–65
UNIT
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
Recommended Operating Conditions (1)
VCC
Operating
Supply voltage
Data retention only
5.5
UNIT
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
MAX
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
TA
(1)
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
10
Operating free-air temperature
mA
–24
VCC = 4.5 V
IOL
V
–55
125
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Product Folder Link(s): SN74LVC1G175-EP
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SN74LVC1G175-EP
SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 mA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.9
IOH = –16 mA
4.5 V
IOL = 100 mA
1.65 V to 5.5 V
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
(1)
0.4
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
V
0.55
4.5 V
VI = 5.5 V or GND
Ci
3.8
3V
IOL = 32 mA
ΔICC
2.3
IOH = –32 mA
IOL = 24 mA
II
V
2.4
3V
IOL = 16 mA
UNIT
VCC – 0.1
IOH = –4 mA
IOH = –24 mA
VOL
MIN TYP (1) MAX
VCC
0.55
0 to 5.5 V
±1
mA
0
±10
mA
1.65 V to 5.5 V
10
mA
500
mA
3 V to 5.5 V
VI = VCC or GND
3.3 V
3
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
tw
Pulse duration
tsu
Setup time, before CLK↑
th
Hold time, data after CLK↑
4
MAX
VCC = 2.5 V
± 0.2 V
MIN
MAX
100
VCC = 3.3 V
± 0.3 V
MIN
125
MAX
VCC = 5 V
± 0.5 V
MIN
150
175
CLR
Low
6.0
3.5
3.2
3.0
CLK
High or low
4.0
3.5
3.2
3.0
3
2.5
2
1.5
0.7
0.7
0.7
0.7
0.7
0.7
0.7
0.7
Data
CLR inactive
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UNIT
MAX
MHz
ns
ns
ns
Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G175-EP
SN74LVC1G175-EP
www.ti.com
SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
VCC = 1.8 V
± 0.15 V
MIN
MAX
100
CLK
Q
CLR
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
125
MIN
MAX
150
VCC = 5 V
± 0.5 V
MIN
UNIT
MAX
175
MHz
2.7
16
2.2
9
1.6
8
1.5
5
2.7
16
2.2
9
1.5
8
1.3
5
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST
CONDITIONS
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
f = 10 MHz
18
19
19
21
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UNIT
pF
5
SN74LVC1G175-EP
SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC1G175-EP
SN74LVC1G175-EP
www.ti.com
SGLS366A – AUGUST 2006 – REVISED DECEMBER 2010
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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Product Folder Link(s): SN74LVC1G175-EP
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2010
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
Samples
(Requires Login)
CLVC1G175MDCKREP
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
CLVC1G175MDCKREPG4
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
V62/06633-01XE
ACTIVE
SC70
DCK
6
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Contact TI Distributor
or Sales Office
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G175-EP :
• Catalog: SN74LVC1G175
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Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2010
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
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Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CLVC1G175MDCKREP
SC70
DCK
6
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
2.24
B0
(mm)
K0
(mm)
P1
(mm)
2.34
1.22
4.0
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Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Feb-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVC1G175MDCKREP
SC70
DCK
6
3000
202.0
201.0
28.0
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Pack Materials-Page 2
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