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Low Capacitance, Low Charge Injection,
±15 V/12 V iCMOS™, Dual SPDT Switch
ADG1236
FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.3 pF off capacitance
3.5 pF on capacitance
1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at +12 V, ±15 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
16-lead TSSOP and 12-lead LFCSP packages
Typical power consumption: <0.03 μW
ADG1236
S1A
D1
S1B
IN1
IN2
S2A
D2
SWITCHES SHOWN FOR A LOGIC 1 INPUT
APPLICATIONS
04776-001
S2B
Figure 1.
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio/video signal routing
Communication systems
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GENERAL DESCRIPTION
The ADG1236 is a monolithic CMOS device containing two
independently selectable SPDT switches. It is designed on an
iCMOS process. iCMOS (industrial CMOS) is a modular
manufacturing process combining high voltage complementary
metal-oxide semiconductor (CMOS) and bipolar technologies.
It enables the development of a wide range of high performance
analog ICs capable of 33 V operation in a footprint that no
previous generation of high voltage parts has been able to
achieve. Unlike analog ICs using conventional CMOS processes,
iCMOS components can tolerate high supply voltages while
providing increased performance, dramatically lower power
consumption, and reduced package size.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked. Both
switches exhibit break-before-make switching action for use in
multiplexer applications.
The ultralow capacitance and charge injection of the part make
it an ideal solution for data acquisition and sample-and-hold
applications, where low glitch and fast settling are required. Fast
switching speed coupled with high signal bandwidth makes the
part suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the part ideally
suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
1.3 pF off capacitance (±15 V supply).
2.
1 pC charge injection.
3.
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8 V.
4.
No VL logic power supply required.
5.
Ultralow power dissipation: <0.03 μW.
6.
16-lead TSSOP and 12-lead 3 mm × 3 mm LFCSP packages.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADG1236
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
Applications....................................................................................... 1
Truth Table for Switches...............................................................6
Functional Block Diagram .............................................................. 1
ESD Caution...................................................................................6
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................7
Product Highlights ........................................................................... 1
Terminology .......................................................................................8
Revision History ............................................................................... 2
Typical Performance Characteristics ..............................................9
Specifications..................................................................................... 3
Test Circuits..................................................................................... 12
Dual Supply ................................................................................... 3
Outline Dimensions ....................................................................... 14
Single Supply ................................................................................. 5
Ordering Guide .......................................................................... 14
REVISION HISTORY
9/05—Revision 0: Initial Version
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Rev. 0 | Page 2 of 16
ADG1236
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
Y Version 1
−40°C to
+85°C
VDD to VSS
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
120
190
3.5
6
20
57
230
260
10
12
72
79
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.02
±0.6
Drain Off Leakage, ID (Off )
±0.1
±0.02
±0.1
±0.02
±0.2
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
−40°C to
+125°C
Test Conditions/Comments 1
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; Figure 20
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
VS = −5 V, 0 V, +5 V; IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
nA typ
VS = ±10 V, VS = ∓10 V; Figure 21
±1
nA max
nA typ
VS = ±10 V, VS = ∓10 V; Figure 21
±0.6
±1
VS = VD = ±10 V; Figure 22
±0.6
±1
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VIN = VINL or VINH
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
pF typ
pF max
pF typ
pF max
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 10 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; Figure 24
VS = 0 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF; Figure 28
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
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2.0
0.8
0.005
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANS AOFF BON
Transition Time, tTRANS BOFF AON
Break-Before-Make Time Delay, tD
2
125
150
70
90
25
200
115
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
CS (Off )
CD, CS (On)
Unit
−1
80
85
0.15
1000
1.3
1.6
3.5
4.3
Rev. 0 | Page 3 of 16
ADG1236
Parameters
POWER REQUIREMENTS
IDD
25°C
Y Version 1
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
IDD
170
230
ISS
0.001
1.0
ISS
0.001
1.0
1
2
Unit
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
Test Conditions/Comments 1
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
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Rev. 0 | Page 4 of 16
ADG1236
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameters
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
25°C
−40°C to
+125°C
0 V to VDD
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Y Version 1
−40°C to
+85°C
300
475
4.5
16
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
567
625
26
27
±0.6
±1
±0.6
±1
±0.6
±1
2.0
0.8
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANS BOFF AON
Transition Time, tTRANS AOFF BON
Break-Before-Make Time Delay, tD
3
105
140
155
190
50
175
255
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS (Off )
POWER REQUIREMENTS
IDD
−0.8
75
85
800
1.6
1.9
4
4.9
0.001
1.0
IDD
170
230
1
2
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −1 mA; Figure 20
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
VS = 1 V/10 V, VD = 10 V/1 V; Figure 21
VS = VD = 1 V or 10 V, Figure 22
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0.001
±0.1
CD, CS (On)
Unit
Temperature range for Y version is −40°C to +125°C.
Guaranteed by design; not subject to production test.
Rev. 0 | Page 5 of 16
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
pF typ
pF max
pF typ
pF max
μA typ
μA max
μA typ
μA max
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS = 8 V; Figure 23
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; Figure 24
VS = 6 V, RS = 0 Ω, CL = 1 nF; Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 26;
RL = 50 Ω, CL = 5 pF, f = 1 MHz; Figure 27
RL = 50 Ω, CL = 5 pF; Figure 28
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
ADG1236
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
Continuous Current per
Channel, S or D
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance
12-Lead LFCSP, θJA Thermal
Impedance
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle max)
25 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
TRUTH TABLE FOR SWITCHES
Table 4.
IN
0
1
Switch A
Off
On
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
80°C/W
260°C
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Over voltages at IN, S, or D are clamped by internal diodes. Current should
be limited to the maximum ratings given.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 16
Switch B
On
Off
ADG1236
15 NC
D1 3
14 NC
ADG1236
13 VDD
TOP VIEW
VSS 5 (Not to Scale) 12 S2B
PIN 1
INDICATOR
ADG1236
8 S2B
VSS 3
TOP VIEW
(Not to Scale)
7 D2
9
IN2
NC = NO CONNECT
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 2. TSSOP Pin Configuration
Figure 3. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
Mnemonic
IN1
S1A
D1
S1B
VSS
GND
NC
IN2
S2A
D2
S2B
VDD
Description
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Negative Power Supply Potential.
Ground (0 V) Reference.
No Connect.
Logic Control Input.
Source Terminal. Can be an input or output.
Drain Terminal. Can be an input or output.
Source Terminal. Can be an input or output.
Most Positive Power Supply Potential.
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Rev. 0 | Page 7 of 16
04776-003
NC 8
NC = NO CONNECT
S2A 6
10 S2A
04776-002
NC 7
IN2 5
11 D2
GND 6
Pin No.
TSSOP
LFCSP
1
11
2
12
3
1
4
2
5
3
6
4
7, 8, 14 to 16 10
9
5
10
6
11
7
12
8
13
9
9 VDD
S1B 2
GND 4
S1B 4
D1 1
11 IN1
16 NC
10 NC
IN1 1
S1A 2
12 S1A
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADG1236
TERMINOLOGY
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
IDD
The positive supply current.
ISS
The negative supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
VD (VS)
The analog voltage on Terminals D and S.
CIN
The digital input capacitance.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
IS (Off)
The source leakage current with the switch off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ID (Off)
The drain leakage current with the switch off.
Off Isolation
A measure of unwanted signal coupling through an off switch.
ID, IS (On)
The channel leakage current with the switch on.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
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VINL
The maximum input voltage for Logic 0.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
VINH
The minimum input voltage for Logic 1.
On Response
The frequency response of the on switch.
IINL (IINH)
The input current of the digital input.
Insertion Loss
The loss due to the on resistance of the switch.
CS (Off)
The off switch source capacitance, measured with reference to
ground.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. 0 | Page 8 of 16
ADG1236
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
TA = 25°C
180
VDD = 13.5V
VSS = –13.5V
200
TA = +125°C
ON RESISTANCE (Ω)
160
140
120
VDD = 16.5V
VSS = –16.5V
100
80
60
100
TA = –40°C
0
–18 –15 –12
–9 –6 –3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
04776-014
04776-011
20
–10
–5
0
5
TEMPERATURE (°C)
10
15
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
600
600
TA = 25°C
VDD = 4.5V
VSS = –4.5V
TA = +125°C
VDD = 12V
VSS = 0V
500
500
VDD = 5V
VSS = –5V
ON RESISTANCE (Ω)
400
TA = +85°C
400
TA = +25°C
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VDD = 5.5V
VSS = –5.5V
300
200
300
TA = –40°C
200
100
0
–6
04776-012
100
–4
–2
0
2
SOURCE OR DRAIN VOLTAGE (V)
4
0
0
6
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
04776-015
ON RESISTANCE (Ω)
TA = +25°C
50
40
2
4
6
8
TEMPERATURE (°C)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
0.20
450
TA = 25°C
400
VDD = 10.8V
VSS = 0V
350
VDD = 12V
VSS = 0V
0.10
LEAKAGE (nA)
300
250
VDD = 13.2V
VSS = 0V
200
VDD = 15V
VSS = –15V
VBIAS = +10V/–10V
0.15
IS (OFF)
0.05
0
–0.05
ID, IS (ON)
150
–0.10
100
–0.15
04776-013
ON RESISTANCE (Ω)
TA = +85°C
150
50
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
–0.20
0
14
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
04776-016
ON RESISTANCE (Ω)
VDD = 15V
VSS = –15V
VDD = 15V
VSS = –15V
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. 0 | Page 9 of 16
ADG1236
0.35
220
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
0.30
200
180
0.25
AOFF BON 12V SS
AOFF BON 15V DS
0.20
140
TIME (ns)
LEAKAGE (nA)
160
0.15
ID, IS (ON)
0.10
120
BOFF AON 12V SS
100
80
0.05
60
IS (OFF)
0
BOFF AON 15V DS
–0.05
–0.10
0
20
40
60
80
TEMPERATURE (°C)
100
04776-004
04776-017
40
20
0
–40
120
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 13. tTRANSITION Times vs. Temperature
60
0
IDD PER CHANNEL
TA = 25°C
–10
50
VDD = 15V
VSS = –15V
TA = 25°C
–20
30
–30
–40
–50
–60
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VDD = 12V
VSS = 0V
10
–80
0
0
2
4
6
8
LOGIC, INX (V)
–70
10
12
–90
–100
10k
14
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 14. Off Isolation vs. Frequency
Figure 11. IDD vs. Logic Level
6
0
TA = 25°C
–10
4
VDD = 15V
VSS = –15V
TA = 25°C
–20
VDD = 15V
VSS = –15V
0
CROSSTALK (dB)
2
VDD = 12V
VSS = 0V
–2
–30
–40
–50
BETWEEN
SA AND SB
–60
–70
–6
–15
–10
–5
0
VBIAS (V)
5
10
BETWEEN
S1 AND S2
–90
–100
10k
15
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Crosstalk vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Rev. 0 | Page 10 of 16
100M
04776-008
–80
–4
04776-005
CHARGE INJECTIOIN (pC)
04776-010
20
04776-018
IDD (μA)
OFF ISOLATION (dB)
VDD = 15V
VSS = –15V
40
1G
ADG1236
5
0
4
CAPACITANCE (pF)
ON RESPONSE (dB)
–5
VDD = 15V
VSS = –15V
TA = 25°C
VDD = 15V
VSS = –15V
TA = 25°C
–10
–15
–20
SOURCE/DRAIN ON
3
2
SOURCE OFF
1
–30
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
0
–15
10G
Figure 16. On Response vs. Frequency
04776-007
04776-009
–25
–10
–5
5
10
15
Figure 18. Capacitance vs. Source Voltage for Dual Supply
5
10.00
LOAD = 10kΩ
TA = 25°C
SOURCE/DRAIN ON
CAPACITANCE (pF)
4
1.00
THD + N (%)
0
VBIAS (V)
VDD = 5V, VSS = –5V, VS = 3.5Vrms
VDD = 15V, VSS = –15V, VS = 5Vrms
VDD = 12V
VSS = 0V
TA = 25°C
3
2
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0.10
SOURCE OFF
0.01
10
100
1k
FREQUENCY (Hz)
10k
04776-006
04776-019
1
0
0
100k
2
4
6
VBIAS (V)
8
10
Figure 19. Capacitance vs. Source Voltage for Single Supply
Figure 17. THD + N vs. Frequency
Rev. 0 | Page 11 of 16
12
ADG1236
TEST CIRCUITS
V
S
IS (OFF)
D
ID (ON)
ID (OFF)
S
A
D
S
NC
A
D
A
Figure 20. Test Circuit 1—On Resistance
VSS
VDD
0.1μF
D
SA
VOUT
RL
300Ω
IN
VIN
CL
35pF
VIN
50%
50%
VIN
50%
50%
90%
VOUT
GND
tON
90%
tOFF
Figure 23. Test Circuit 4—Switching Times
0.1μF
VDD
VSS
0.1μF
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SB
VS
VIN
VSS
VDD
D
SA
VOUT
RL
300Ω
IN
VOUT
CL
35pF
80%
tBBM
VIN
tBBM
04776-024
GND
Figure 24. Test Circuit 5—Break-Before-Make Time Delay
VDD
VSS
VDD
VSS
0.1μF
VIN (NORMALLY
CLOSED SWITCH)
ON
SB
VS
NC
D
VOUT
SA
CL
1nF
IN
VIN
GND
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
ΔVOUT
QINJ = CL × ΔVOUT
Figure 25. Test Circuit 6—Charge Injection
Rev. 0 | Page 12 of 16
04776-025
0.1μF
VD
Figure 22. Test Circuit 3—On Leakage
VSS
SB
VS
NC = NO CONNECT
Figure 21. Test Circuit 2—Off Resistance
VDD
0.1μF
VD
04776-022
VS
04776-023
VS
04776-021
04776-020
IDS
ADG1236
VDD
VDD
VSS
0.1μF
VDD
NC
SA
IN
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
SB
50Ω
VDD
RL
50Ω
50Ω
SB
VS
D
VIN
RL
50Ω
R
50Ω
VS
GND
04776-026
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 26. Test Circuit 7—Off Isolation
VDD
D
IN
VOUT
GND
OFF ISOLATION = 20 log
VSS
SA
VOUT
04776-028
0.1μF
VOUT
VS
Figure 28. Test Circuit 9—Bandwidth
VSS
0.1μF
VDD
NC
SA
VDD
NETWORK
ANALYZER
VSS
SB
VSS
0.1μF
0.1μF
50Ω
AUDIO PRECISION
VDD
50Ω
VSS
RS
VS
S
D
VIN
GND
IN
VOUT
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RL
50Ω
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
04776-027
VIN
INSERTION LOSS = 20 log
VS
V p-p
D
RL
10kΩ
VOUT
GND
Figure 27. Test Circuit 8—Channel-to-Channel Crosstalk
Figure 29. Test Circuit 10—THD + Noise
Rev. 0 | Page 13 of 16
04776-029
0.1μF
IN
VSS
0.1μF
0.1μF
ADG1236
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153AB
Figure 30. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
3.00
BSC SQ
0.75
0.55
0.35
0.60 MAX
PIN 1
INDICATOR
*1.45
1.30 SQ
1.15
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0.45
PIN 1
INDICATOR
9
2.75
BSC SQ
TOP
VIEW
10 11 12
8
2
7
6
EXPOSED PAD
(BOTTOM VIEW)
SEATING
PLANE
5
4
3
0.25 MIN
0.50
BSC
0.80 MAX
0.65 TYP
12 MAX
1.00
0.85
0.80
1
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 31. 12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-12-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG1236YRUZ 1
ADG1236YRUZ-REEL1
ADG1236YRUZ-REEL71
ADG1236YCPZ-500RL71
ADG1236YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
12-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Z = Pb-free part.
Rev. 0 | Page 14 of 16
Package Option
RU-16
RU-16
RU-16
CP-12-1
CP-12-1
ADG1236
NOTES
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Rev. 0 | Page 15 of 16
ADG1236
NOTES
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© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04776–0–9/05(0)
Rev. 0 | Page 16 of 16