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A 3.3-to-25V all-digital charge pump based system with temperature and load compensation
for avalanche photodiode cameras with fixed sensitivity
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2013 JINST 8 P03013
(http://iopscience.iop.org/1748-0221/8/03/P03013)
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P UBLISHED BY IOP P UBLISHING FOR S ISSA M EDIALAB
R ECEIVED: December 31, 2012
ACCEPTED: February 18, 2013
P UBLISHED: March 19, 2013
S. Mandai1 and E. Charbon
Faculty of Electrical Engineering, Delft University of Technology,
Mekelweg 4, 2628 CD Delft, The Netherlands
E-mail: [email protected]
A BSTRACT: This paper presents a digitally controlled charge pump (DCP) to supply high voltages, while ensuring temperature and load current independence of excess bias in cameras based
on avalanche photodiodes. This is achieved through a single-photon avalanche diode (SPAD) based
monitoring mechanism that continuously reconfigures the DCP using a feedback loop to compensate breakdown voltage variations by temperature and load current in real time. The sensitivity of
the SPADs, or photon detection probability (PDP), is maintained to within 1.9% when the temperature shifts from 28◦ C to 65◦ C and the load current changes from 0 µA to 100 µA.
K EYWORDS : VLSI circuits; Analogue electronic circuits; Detector control systems (detector and
experiment monitoring and slow-control systems, architecture, hardware, algorithms, databases);
Digital electronic circuits
1 Corresponding
author.
c 2013 IOP Publishing Ltd and Sissa Medialab srl
doi:10.1088/1748-0221/8/03/P03013
2013 JINST 8 P03013
A 3.3-to-25V all-digital charge pump based system
with temperature and load compensation for
avalanche photodiode cameras with fixed sensitivity
Contents
Introduction
1
2
Architecture and implementation
2.1 System architecture
2.2 Digitally controlled charge pump
2.3 Environment monitor
3
3
3
3
3
DCP and environment monitor characterization
3.1 Chip fabrication
3.2 DCP characterization
3.3 Environmental monitor characterization
5
5
5
6
4
System operation
4.1 System setup
4.2 Interpolation method for excess bias and temperature information
4.3 System characterization
7
7
7
9
5
Conclusion
9
1
Introduction
Single-photon avalanche diodes (SPADs) are used as imaging devices in various fields, including
molecular imaging, 3-D vision, space exploration, security monitoring, and biomedical diagnostics. SPADs need to be reverse-biased several volts above breakdown; these voltages are far beyond
the transistor’s operation conditions. Charge pumps based on the Dickson architecture are widely
used to supply a high voltage proportional to the number of stages [1, 2]; these circuits are ideally suited for a SPAD biasing for bill-of-materials and cost reduction [3, 4]. Figure 1 shows the
concept of a sensor based on a SPAD array with charge pump: each pixel consists of a SPAD, a
current source, and ancillary circuitry. The cathode of the SPAD is biased to Vop , = Vbd +Ve , where
Vbd is the breakdown voltage and Ve the excess bias. The anode, Vpix , is connected to an active
quenching circuit used to stop an avalanche quickly enough to prevent device destruction with a
long enough hold-up time to enable detection. During the detection cycle, Vpix reaches Ve in less
than 1 ns and returns to ground absorbing a current pulse Isource (t), upon a photon or thermal event.
The width of the pulse is proportional to Ve and the sum of all impulsive currents, Isum , is proportional to the illumination brightness and must thus be guaranteed by the voltage generator under all
specified lighting conditions. In addition, the generator must also adjust Vop to maintain a constant
excess bias when the breakdown voltage changes, due to process and temperature variations and
–1–
2013 JINST 8 P03013
1
Vop = Vbd + Ve
Vpix
Charge
pump
Isum = ∑ ISPAD
Ve
ISPAD
SPAD
pixel
Pixel
circuit
Vpix
Isum (Brightness)
Isum (Dark)
SPAD based pixel array
Time
(b)
(a)
Environmental effects
Load current change
(Brightness change)
Sen
Ve
Vbd
sitiv
ity
< Ve
Vop
Vop
+
Breakdown shift
(Temperature shift)
-
Load current
(c)
+
Sensitivity
> Ve
Ve
< Ve
Vbd
Temperature
(d)
Figure 1. (a) Concept of a SPAD array with excess bias voltage stabilization via charge pump. (b) Superimposed oscilloscope traces of pixel responses. (c),(d) Typical response of conventional charge pump output
as a function of load current and temperature with respect to breakdown voltage Vbd . Sensitivity varies with
excess bias and thus it will degrade with an increase temperature and load current, if measures are not taken.
to account for current absorption variations at Vop due to increase of brightness [3, 4]. The charge
pump proposed in [5] is insensitive to current variations but still the charge pump is sensitive to
temperature fluctuation. Thus maintaining the excess bias irrespective of process, voltage, temperature, and brightness (PVT-B) variations is essential to ensure constant and reliable sensitivity
levels of SPAD arrays over long periods of time, as demanded by today’s applications.
This paper presents a digitally controlled charge pump (DCP) based system to supply high
voltages, while assuring PVT-B independence of excess bias in large SPAD arrays. This is achieved
through a SPAD-based environment monitoring mechanism that continuously reconfigures the
DCP using a feedback loop to compensate for temperature and breakdown voltage variations in
real time. The sensitivity of the SPADs, or photon detection probability (PDP), is maintained to
within 1.9% when the temperature shifts from 28◦ C to 65◦ C and the load current changes from 0
to 100 µA.
The paper is organized as follows. Section 2 shows the architecture and circuit implementation. Section 3 presents each component’s characterization and section 4 demonstrates the system
operation. Finally, conclusions are given in section 5.
–2–
2013 JINST 8 P03013
ISPAD
Isource
Photon hit or Noise
2
2.1
Architecture and implementation
System architecture
Excess bias is estimated utilizing dark count rate (DCR) and the pulse width of SPAD output. DCR
is a function of the temperature and excess bias, being shown as DCR = f (T,Ve ) using temperature,
T, and excess bias Ve . The pulse width, PW, is calculated using the SPAD capacitance, Cspad , and
current source, Isource assuming that the parasitic capacitances of the peripheral circuit of SPADs
are small, as shown, PW = Ve × C(T )/Isource (T ). Therefore, excess bias is the solution of the
simultaneous equation shown below,
(2.1)
PW = g(T,Ve )
(2.2)
In this system, after estimating the excess bias by observing DCR and pulse width using a DCR
counter and a pulse-width-to-digital converter (PWDC), DCP is reconfigured according to the estimation to keep the excess bias constant. This procedure will be iterated in real time to adapt a
dynamic environment change.
2.2
Digitally controlled charge pump
Figure 2 shows the schematic of the DCP; it is clocked by a 6-bit digital controlled oscillator
(DCO), whose frequency can be swept from 43.7 MHz to 1.2 GHz. The DCP resembles a 11-stage
Dickson architecture, except for a parasitic capacitance, Cparasitic , in each stage that can be digitally
modulated via NMOS switches. The voltage gain in each stage is (Vdd −Vt )C/(Cparasitic +C), where
Vdd is the power supply, Vt the threshold voltage of the stage’s diode, and C, the main capacitance.
The input voltage of the DCP is 3.3 V, the nominal power supply voltage, and C is 1.64 pF. The
DCP output voltage modulation step is approximately 80 mV and it depends on the DCP frequency
and Isum . This voltage step was chosen as 1% of the detector sensitivity.
2.3
Environment monitor
Figure 3 shows a schematic of the environment monitor. The monitor acquires the dark counts
and computes the dark count rate (DCR) of a reference SPAD that was shielded from light; it
also measures the width of the avalanche pulses of the SPAD. The width of the avalanche pulse
is proportional to the excess bias, the SPAD capacitance and a FPGA-controlled capacitance. The
latter is used to enlarge the avalanche pulse, which looks like a sawtooth, to make it easier to
measure its width. The avalanche pulse is converted onto a square wave, EN, by a comparator and
digitized to a digital code with the PWDC. The PWDC consists of 4-stage differential inverter chain
with a 10-bit counter; the inverter chain oscillates when EN in on. The frequency of oscillation is
the inverse of the timing resolution, which in turn is dynamically checked by the replica PWDC
that is fed a reference pulse generated by a temperature independent PLL on a FPGA. The DCR and
avalanche pulse width will be used to estimate the temperature and the excess bias of the SPAD.
There are three identical environment monitors operating in parallel to increase the estimation
speed and to cope with low DCR.
–3–
2013 JINST 8 P03013
DCR = f (T,Ve )
Digital charge pump structure
DCO control code
CLK
DCO
VIN
DCP
VOP
DCP control
code
Digital controlled
oscillator (DCO)
Digitally controlled
charge pump (DCP)
VIN
VOP
D0
D5
D0
D5
D0
Csum
D5
Digitally controlled Inverter
D0
D1
D2
CLK
D3
D4
CLK
Digitally controlled
capacitance
C/100
OUT
C/25
C/50
E0
D0
D1
D2
D3
D4
E1
C/6.25
C
C/12.5
E2
E3
E4
D5
Cparasitic
CLK
Figure 2. Block diagram of the digitally controlled charge pump and schematics of its components. DCO
is a three-stage digitally controlled ring oscillator by changing the number of current sources. DCP is also
digitally controlled to change the ratio of the peripheral capacitance by NMOS switches.
Reference pulse
Excess bias Detector replica
Excess bias Detector #3
Excess bias Detector #2
Excess bais Detector #1
VOP
Pulse output
MUX
Shielded
SPAD
VREF
EN
100fF
DC0
Readout
circuit
200fF
DC1
Pulse-width-to-digital converter
CNT
RST
RST
RST
RST
PH<0> EN
PH<1>
EN
PH<2> EN
PH<3> EN
PH<0> EN
PH<1>
EN
PH<2> EN
PH<3> EN
RST
RST
RST
PH<3>
RST RST
IN OUT
CNTOUT
RST
Figure 3. Schematic of the environment monitor, comprising an array of shielded SPADs, a comparator, the
pulse-width-to-digital converter, and readout circuitry.
–4–
2013 JINST 8 P03013
IN
D5
Fixed
capacitance
Programable
parasitic
capacitance
2.8 mm
Readout
Pulse width
detector
DCP
DCO
SPAD
0.36 mm
DCO
Clock
buffer
Divider for
frequency monitor
Figure 4. Chip microphotograph. Details of the circuit are shown in the insets. The chip measures 2.8 ×
0.36 mm2 and it was fabricated in a commercial 0.35 µm CMOS process.
3
3.1
DCP and environment monitor characterization
Chip fabrication
The DCP and the environment monitor have been designed and fabricated using a 2P4M high
voltage 0.35 µm CMOS process. A photomicrograph of the chip is shown in figure 4. The figure
shows the die size is 0.36 × 2.7 mm2 . The 6 µm diameter SPAD comprises a p+ / deep n-well
junction with a p-well guard ring [6]. The breakdown voltage at 20◦ C is 19.6 V. The quenching
current source generates 15 µA.
3.2
DCP characterization
The DCP was characterized first in open-loop and subsequently in closed-loop, with a controlled
load current and temperature. Figure 5 (a) shows the DCP output voltage plotted as a function of
DCO clock frequency and control coding in an open-loop operation mode. DCO and DCP control
code are corresponding to D5-D0 and E4-E0 in figure 2. DCO frequency is swept with 720 ns step
and the DCP output voltage becomes stable within 720 ns. Figure 5 (b) shows the DCP output
voltage as a function of clock frequency for selected codes; one can see that the maximum voltage
is achieved at one optimal clock frequency. Figure 5 (c) shows that the optimal frequency shifts
up by increasing loading for a given control code, while figure 5 (d) shows how the DCP output
voltage varies with different control codes by changing the loading, when the DCP is operated at
the optimal clock frequency for that loading level.
–5–
2013 JINST 8 P03013
Environment
Monitor
25
OUTPUT of DCP (V)
0-29
24
(-)
DCP
con
trol
e(
cod
)
DCP control code
(+)
24
OUTPUT of DCP (V)
25
23
DCO frequency
(6-25 : 122MHz-650MHz)
22
28
24
23
20
16
22
12
8
4
0
21
Each step is less than 720 ns
21
50
100
150
200 250
Time (μs)
300
350
400
100
200
300
400
DCP frequency (MHz)
(a)
500
(b)
25
25
Optimal frequency
21
0A
20
uA
OUTPUT of DCP (V)
22
40u
A
A
23
24
60u
OUTPUT of DCP (V)
24
0A
23
20u
22
40u
A
60u
21
20
A
A
20
100
200
300
400
DCP frequency (MHz)
500
0
(c)
10
20
30
40
DCP control signal
50
(d)
Figure 5. Measurement results of the digitally controlled charge pump (DCP). (a) Transient sweeping of
the DCO clock frequency and DCP control code. (b) DCP output voltage as a function of DCO frequency
and DCP control code. (c), (d) DCP output voltage as a function of DCO frequency for a given DCP code at
various loading levels.
3.3
Environmental monitor characterization
The resolution of PWDC is 204 ps at 20◦ C , and has a INL of +0.5 / -1.6 LSB in 1.24 µs input
range; note that the typical single-shot jitter is 1.6 LSB (FWHM). The resolution improves by
4.1 ps and 4.3 ps by cooling the device to 10◦ C and by increasing the power supply voltage by 0.1 V,
respectively. Figure 6 (a) plots the pulse width histogram of SPAD avalanche pulses occurred in
153 seconds and measured by the PWDC at several excess bias values from 1.5 V to 3.5 V with a
0.5 V step, spanning a temperature range from 0◦ C to 70◦ C with a 10◦ C step. The average FWHM
of the pulse width is 13.8 ns, corresponding to 115 mV of excess bias and 21.6◦ C temperature
resolution. By averaging the results over 200 iterations, the FWHM can be improved to 3.47 ns,
corresponding to 28.9 mV of excess bias and 5.4◦ C temperature resolution. The estimation time is
limited by DCR, the DCR being less than 10 Hz at lower temperatures. Figure 6 (b) summarizes
the relation between DCR and pulse width at various temperature and excess bias combinations.
By utilizing a DCR and pulse width map, intermediate temperature and excess bias values can be
accurately estimated by way of interpolation. Figure 6 (c) summarizes the relations between pulse
width, DCR, temperature, and excess bias.
–6–
2013 JINST 8 P03013
20
0
(#) : FWHM
100
Excess bias
dependence
80
60
2V
1.5V (14.9)
(12.2)
40
20
10000
3.5V
(14.3)
3.5V
3.0V
Excess
2.5V
bias 2.0V
1000 1.5V
3V
2.5V (14.5)
(13.3)
0
0
100
200
300
400
500
600
(a)
70℃ 60℃
(14.2) (13.4)
Temperature
100
50℃
dependence
(13.0) 40℃
(13.8) 30℃ 20℃
(14.8)(14.5) 10℃ 0℃
(19.4) (14.4)
1000
100
50℃
40℃
30℃
20℃
10℃
0℃
10
10
1
1
300
320
340
360
380
400
100
200
300
400
500
Pulse width (ns)
Pulse width detector digital code (LSB)
(c)
(b)
Figure 6. Estimation of avalanche pulse width and excess bias in various environmental conditions. (a)
Pulse width histograms as a function of excess biases and temperature; in parentheses the FWHM jitter of
the measurement. (b) Pulse width histograms as a function of DCR for various temperatures; note that low
DCRs result in worse width estimation uncertainties, shown in parentheses. (c) Pulse width estimation vs.
DCR for various combinations of excess bias and temperature.
4
4.1
System operation
System setup
The DCP was tested in closed-loop configuration, whereas the environment monitor is used in
the feedback. Figure 7 (a) shows the block diagram for the feedback loop. The SPAD array is
emulated by a variable current source. The DCP output is provided to three SPAD cathodes. All
SPAD outputs are read out and monitored by FPGA, simultaneously, the SPAD outputs are rectified
and converted to digital codes by a bank of PWDCs. The DCR calculator counts the count rate and
the Pulse width calculator takes averages of the pulse width. The PWDC is dynamically calibrated
using a replica pulse from a temperature-insensitive PLL in the FPGA. FPGA and host PC estimate
the excess bias of the SPADs using a look-up table (LUT) which has been pre-calculated during a
calibration phase. Based on the estimation, the proper digital code for DCP and DCO is generated
and available from the FPGA. Figure 7 (b) shows the timing diagram of the system. The system
clock frequency is 20 MHz. After reset, the replica pulse is generated. Once one of the SPADs
fires, the FPGA starts to read out the latched data of all PWDCs in 26 clock cycles. Then, the
system again waits until the next dark count occurs in an event driven scheme.
4.2
Interpolation method for excess bias and temperature information
Figure 8 shows the excess bias and temperature information estimation based on LUT acquired
beforehand. To acquire excess bias and temperature information based on interpolation method,
the parameter, α and β should be solved using measured vector ~x, and temperature direction, and
–7–
2013 JINST 8 P03013
Count rate (Hz)
10000
70℃
60℃
DCR (Hz)
Count rate (Hz)
120
Environment monitor
CLKB
CLK
Shield
Vop
DCP
Vin
Replica
pulse
DCR calculator
Frequency control
signal (Digital)
DCP & DCO
controller
PWDC
Readout
Pulse width
calculator
LUT
FPGA & host PC
Data
Request
(a)
50ns 50ns
62 clock cycles
CLK
RST
Replica
pulse
80ns
Vpix
Pulse width
LATCH
FPGA detect the pulse and
latch the data immediately
pulse width data
Readout
(b)
Figure 7. Feedback operation detail and extra measurement results. (a) Block diagram for the feedback
loop. (b) Timing diagram. The readout circuit starts to read out as soon as the FPGA detects the DCR pulse.
The minimum number of clock cycles to read out the data from three PWDCs and the replica PWDC, is 62.
excess bias direction vector, ~a and ~b, from the equations shown below,
~x = α~a + β~b.
By assuming that ~a = (∆PWa , ∆DCRa ), ~b = (∆PWb , ∆DCRb ) and~x = (∆PWx , ∆DCRx ), α and β can
be calculated as below,
α =
DCRb PWx − PWb DCRx
PWa DCRb − PWb DCRa
(4.1)
β =
DCRa PWx − PWa DCRx
PWb DCRa − PWa DCRb
(4.2)
–8–
2013 JINST 8 P03013
Excess bias
estimator
PWDC
SPAD array
emulator
PWDC
DCO
PWDC
DCP control
signal
(Digital)
10000
DCR (Hz)
1000
(T+ΔT, Ve)
Excess
bias 2.0V
1.5V
2.5V
100
3.0V
3.5V
(Tx, Vex)
70℃
b
60℃
50℃
40℃
30℃
20℃
10℃
0℃
x
10
b
100
200
300
400
Pulse width (ns)
500
(PW, DCR)
(PW+αPWx,
DCR+βDCRx)
x
a
(PW+ΔPWa,
DCR+ΔDCRa)
Figure 8. Interpolation method to acquire excess bias and temperature information using coarse calibration
data.
Then current excess bias, Vex , and current temperature, Tx , are calculated using excess bias
step, ∆Ve , and temperature step, ∆T , based on the course calibration beforehand (figure 6 (c) and
figure 8) as below
4.3
Vex = Ve + α × ∆Ve
(4.3)
Tx = T + β × ∆T
(4.4)
System characterization
Figure 9 (a) and (b) show the measured excess bias with and without feedback. The excess bias
is reconfigured in real time when temperature or load current are dynamically changed with the
feedback loop described above. The resulting estimated excess bias derived from the LUT is also
drawn in the same graph. The average excess bias difference between measurement and estimation
is 78 mV and 60 mV for the temperature and the load current sweep, respectively. A voltage variation of 5.7% and 3.7% were measured with feedback when the temperature ranged from 28◦ C to
65◦ C and the load current from 0 A to 100 µA, respectively versus a 10.3% and 68% variation without feedback. With feedback the variation in sensitivity was only 1.9% at a wavelength of 450 nm
in the entire temperature range. Figure 9 (c) summarizes the features of the proposed high-voltage
generator and compares it with the literature [2, 3, 5].
5
Conclusion
We have presented a digitally controlled charge pump (DCP) to supply high voltages, while ensuring temperature and load current independence of excess bias in cameras based on avalanche
photodiodes. This is achieved through a single-photon avalanche diode (SPAD) based monitoring
mechanism that continuously reconfigures the DCP using a feedback loop to compensate breakdown voltage variations by temperature and load current in real time. The sensitivity of the SPADs,
or photon detection probability (PDP), is maintained to within 1.9% when the temperature shifts
from 28◦ C to 65◦ C and the load current changes from 0 µA to 100 µA.
–9–
2013 JINST 8 P03013
1
(T, Ve+ΔVe)
(T, Ve)
(PW+ΔPWb,
DCR+ΔDCRb)
a
28℃
3.15
3.5
w/i feedback (Measured)
Excess bias (V) : 2.91-3.08
Voltage variation : 5.7%
3.10
3.0
w/i feedback
(Estimated)
2.5
Excess bias (V)
3.05
Excess bias (V)
w/i feedback (Measured)
Excess bias (V) : 2.98-3.09
Voltage variation : 3.7%
65℃
3.00
w/i feedback
(Estimated)
2.95
2.90
w/o feedback (Measured)
Excess bias (V) : 2.82-3.13
Voltage variation : 10.3%
2.85
2.0
1.0
0.5
2.80
0
400
Time (s)
600
800
0
20
40
60
Load curret (μA)
(a)
80
100
(b)
Features
This work
[2]
[3]
[5]
Technology
350 nm
130nm
90nm
180nm
Area
0.36 mm x 2.8 mm
0.3 mm x 0.1 mm
0.12 mm x 0.16 mm
2.05 mm x 1.95 mm
Output voltage
21.4 V - 25 V
1.2 V to 8V
10.9 V
1.2 V - 6 V
Application
SPAD based camera
Non-volatile memory
SPAD based camera
Earphone
Current change
Insensitive
Sensitive
Sensitive
Insensitive
Temperature shift
Insensitive
Sensitive
Sensitive
Sensitive
(c)
Figure 9. Excess bias voltage control results with and without feedback (a) as a function of temperature and
(b) load current. (c) Specification summary and comparison with literature.
Acknowledgments
The authors would like to thank Dr. M.W. Fishburn of TU Delft for many useful discussions.
References
[1] J.F. Dickson, On-chip high-voltage generation in MNOS integrated circuits using an improved voltage
multiplier technique, IEEE J. Solid State Circ. 11 (1976) 374.
[2] A. Richelli, L. Mensi, L. Colalongo, P.L. Rolandi and Z.M. Kovacs-Vajna, A 1.2-to-8V Charge-Pump
with Improved Power Efficiency for Non-Volatile Memories, IEEE Solid State Circ. Conf. 2007 (2007)
552.
[3] R.K. Henderson, E.A.G. Webster, R. Walker, J.A. Richardson and L.A. Grant, A 3 × 3, 5 µm pitch,
3-transistor Single Photon Avalanche Diode Array with Integrated 11V Bias Generation in 90 nm
CMOS Technology, IEEE Int. Electron Dev. Meeting 2010 (2010) 14.2.1.
[4] M. Al-Rawhani, D. Cumming, D. Chitnis and S. Collins, Photocurrent Dependent Response of a SPAD
biased by a charge pump, IEEE Int. Symp. Sirc. Syst. ISCAS 2009 (2011) 789.
[5] C.Y. Tseng, S.C. Chen, T.K. Shia and P.C. Huang, An Integrated 1.2V-to-6V CMOS Charge-Pump for
Electret Earphone, IEEE Symp. VLSI Circ. 2007 (2007) 102.
[6] C. Niclass, C. Favi, T. Kluter, M.A. Gersbach and E. Charbon, A 128 × 128 single-photon image sensor
with column-level 10-bit time-to- digital converter array, IEEE J. Solid State Circ. 43 (2008) 2977.
– 10 –
2013 JINST 8 P03013
200
0
w/o feedback (Measured)
Excess bias (V) : 1.09-3.13
Voltage variation : 68%
1.5