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CHAPTER 6: MOSFET & RELATED DEVICES Part 1 MOSFET and Related Devices 6.1 The MOS diode 6.2 MOSFET fundamentals 6.3 MOSFET scaling 6.4 CMOS and BiCMOS 6.5 MOSFET on insulator 6.6 MOS memory structures 6.7 The power MOSFET THE MOS DIODES Figure 6.1. (a) Perspective view of a metal-oxide-semiconductor (MOS) diode. (b) Cross-section of an MOS diode. THE MOS DIODES (cont.) Figure 6.2. Energy band diagram of an ideal MOS diode at V = 0. • KEYWORDS : a) Work Function, : Energy difference between the Fermi level and the vacuum level. b) Electron affinity, : Energy difference between the conduction band edge and the vacuum level in the semiconductor. c) : Energy difference between the Fermi level EF and the intrinsic Fermi level Ei THE MOS DIODES (cont.) An ideal MOS is defined as follows: a) At zero applied bias, the energy difference between the metal work function (qm) and the semiconductor work function (qs) is zero or the work function difference (qms) is zero qm qm qs Eg qm q q B 0 2 # The energy band is flat (flat band condition) when (1) there is no applied voltage b) The only charges that exist in the diode under any biasing conditions are those in the semiconductor and those with equal but opposite sign on the metal surface adjacent to the oxide. c) There is no carrier transport through the oxide under direct current (dc) - biasing condition or the resistivity of the oxide is infinite. THE MOS DIODES CASES (cont.) a) ACCUMULATION CASE : - V<0 is applied to the metal plate, holes will be induced at the SiO2 – Si interface. - Bands near the semiconductor surface are bent upward. It cause an increase in the energy Ei-EF which in turn gives rise to an enhanced concentration and accumulation of holes near the oxidesemiconductor interface - No current flows. b) DEPLETION CASE : - V>0 is applied, the energy bands near the semiconductor surface are bent downward. - Holes (majority carriers) are depleted. ENERGY BAND DIAGRAMS AND CHARGE DISTRIBUTIONS OF AN IDEAL MOS DIODE THE MOS DIODES (cont.) c) INVERSION CASE : Larger positive voltage applied, energy bands bend downward even more so the Ei at the surface crosses over the Fermi level. The positive gate voltage starts to induce excess electrons at the SiO2 – Si interface. Electrons greater than holes, thus the surface is inverted. Carrier density (holes) depends on energy difference n p ni e( EF Ei ) / kT THE MOS DIODES (cont.) The surface depletion region Figure 6.4. Energy band diagrams at the surface of a p-type semiconductor. (electrostatic potential)=0 (in bulk) s (surface potential)= (at s/c surface) Electron concentration Hole concentration n p ni e ( EF Ei ) / kT (2) p p ni e( Ei EF ) / kT Expressed as a function of (3) See eq. (4) & (5) np ni e q ( B ) / kT p p ni e q ( B ) / kT ns ni e q ( s B ) / kT ps ni e q ( B s ) / kT (4) is positive when the (5) band is bent downward (6) Densities at the surface (7) The following regions of surface potential can be distinguished: s0 Accumulation of holes (bands bend upward) s=0 Flat-band condition Bs0 Depletion of holes (bands bend downward) s=B Midgap with ns=np=ni (intrinsic concen.) s>B Inversion (bands bend downward) d 2 s ( x) 2 dx s as a function of distance (1D poisons eq.) s(x) : charge density per unit volume s : dielectric permittivity (7) When the semiconductor is depleted to a width of W and the charge within the semiconductor is given by s qN A , Electrostatic potential at surface depletion region: qN AW 2 s 2 s (8) Note: Potential distribution = one sided n+ -p junction The surface is inverted whenever sB ns (e concen. at surface)= nA (substrate impurity concentration) s (inv) 2B Maximum width of the surface depletion region Wm: Qsc qN AWm 2q s N A (2 B ) 2kT N A ln q ni Wm 2 s s (inv ) qN A N s kT ln A ni Wm 2 q2 N A (9) 2 s (2 B ) qN A (10) Example For an ideal metal-SiO2-Si diode having NA=1017cm-3, calculate the maximum width of the surface depletion region Solution: At room temp. kT/q=0.026 and ni=9.65x109cm-3, the dielectric permittivity of Si is 11.9x8.85x10-14F/cm Wm 2 17 11.9 8.85 10 14 0.026 ln 10 1.6 10 19 1017 10 5 cm 0.1m Figure 6.5. Maximum depletion-layer width versus impurity concentration of Si and GaAs under strong-inversion condition. 9.65 109 Ideal MOS Curves No work function differences – applied voltage appear partly across oxide & across semiconductor V Vo S Vo o d QS d ox QS Co Vo Potential across the oxide o Field in the oxide QS Charge per unit area Co Oxide capacitance per unit area (a) Band diagram of an ideal MOS diode. (b) Charge distributions under inversion condition. (c) Electric field distribution. (d) Potential distribution C Total capacitance of MOS diode Co Oxide capacitance Cj Semiconductor depletion-layer capacitance C Co C j (Co C j ) Co W Width of depletion o Permittivity in vacuum ox Insulator permittivity Cj F / cm 2 ox d s W (a) High-frequency MOS C-V curve showing its approximated segments (dashed lines). Inset shows the series connection of the capacitors. (b) Effect of frequency on the C-V curve.2 Threshold voltage: 2 s qN A (2 B ) qN AWm VT s (inv) 2 B Co Co Minimum value of total capacitance: Cmin ox d 0 x Wm s The SiO2 – Si MOS diode Metal-SiO2-Si : most extensively studied Work function difference qms 0 (for metal electrodes) Work function semiconductor qs (Energy difference: Between vacuum level – Fermi level) Work function metal qm difference: qms (qms - qs) Aluminum : qm = 4.1eV Polysilicon : n+ qm = 4.05eV p+ qm = 5.05eV Work function difference as a function of background impurity concentration for Al, n+-, and p+ polysilicon gate materials. To construct energy band diagram (in the figure) In the isolated metal & semiconductor – all bands are flat At thermal equilibrium: constant Fermi level & continuous vacuum level. At thermal equilibrium: metal +ve charge semiconductor surface –ve charge To get ideal flat band: apply a voltage = qms So apply –ve voltage VFB to metal flat band voltage (VFB = ms) (a) Energy band diagram of an isolated metal and an isolated semiconductor with an oxide layer between them. (b) Energy band diagram of an MOS diode in thermal equilibrium. Interface Traps & Oxide Charges MOS diode is affected by charges in the oxide & traps in the SiO2-Si interface Classifications of traps & charges: Interface-trapped charge Fixed oxide charge Oxide trapped charge Mobile ionic charge Interface trapped charge Qit due to SiO2-Si interface properties & chemical composition in the interface Location: SiO2-Si Interface trap density (number of interface traps per unit area & per eV) in 100 the interface trap density is an order of magnitude smaller than 111 Fixed charge, Qf Location: within 3nm of the SiO2-Si interface The charge is fixed – cannot be charged or discharged Qf is generally +ve & can be regarded as a charge sheet located at the SiO2-Si interface Oxide-trapped charges, Qot Associated with defects in SiO2 The charges can be created (Eg. by X-ray radiation or high energy electron bombardment) – traps are distributed inside the oxide layer. Can be removed by low temperature annealing Mobile ionic charges, Qm Eg. Sodium & alkali ions – mobile under raised-temperature (Eg. >100oC) & high field operations. Stability problem in semiconductor devices operated under high bias & high temperature conditions Mobile ion charges move back & forth through the oxide layer cause shifts of CV curves along voltage axis Mobile ions have to be eliminated Evaluate the effective net charges per unit area (C/cm2) on the flat band voltage Consider a +ve sheet charge per unit area Qo within the oxide induce –ve charges (partly in metal, partly in semicond.) (fig. (a)) Resulting field distribution assumed that there is no work function difference (qms=0) To reach a flat band condition (no charge induced) apply –ve voltage to metal (fig. (b)) As –ve voltage increases more –ve charges on the metal electric field distribution shift downward until the electric field is zero (at surface) Area contained under the electric field distribution corresponds to the flat-band voltage VFB : Effect of a sheet charge within the oxide. (a) Condition for VG = 0. (b) Flat-band condition. VFB o xo Qo ox xo Qo xo Co d Qo Density of the sheet charge xo Location within the oxide When sheet charge very close to metal if xo=0 : induce no charges, no effect on the flat band voltage When Qo very close to semiconductor xo=d : it will exert its max influence, give rise to a flat band voltage: Q d Q VFB o o Co d Co Arbitrary space charge distribution within the oxide: (x) : volume charge density in the oxide ot(x) : volume charge density for oxide-trapped charges m(x) : volume charge density for mobile ionic charges 1 d Qot x ot ( x)dx d o 1 d Qm x m ( x)dx d o If qms0 & interface-trapped charges is negligible experimental C-V curve will be shifted from the ideal theoretical curve by an amount : VFB ms (Q f Qm Qot ) Co Important! Effect of a fixed oxide charge and interface traps on the C-V characteristics of an MOS diode.