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Networked Embedded Systems Dipartimento di Informatica - Università di Verona The HW/SW/Network Cosimulation-based Design Flow Introduction Transaction Level Modeling (TLM) HW/SW/Network design flow Case study: V-CLIP V-CLIP: refinement steps HW/SW – Network interfaces Introduction Networked embedded systems represent an important class of digital systems routers, wireless access points, wireless sensor networks, mobile phones, etc. Aspects to be modeled and simulated: Hardware Software Network Different design and modeling tools should be combined HW/SW/Network co-design and co-simulation framework 2 TLM: Transaction Level Modeling TL3 TLM Refinement Algo (specifications) TL2 TL1 TLM RTL Synthesis 3 TLM: Transaction Level Modeling Level TL3 Use Features Executable specifications and first level of functional partitioning of data and control. Implementation architecture-abstract. System proof of concepts. Event-driven simulation semantics. Untimed functionalities modeling. Point-to-point Initiator-Target connection. Abstract data types. TL2 Hardware architectural performance and detailed behavior analysis. Mapping ideal architecture into resource-constrained world. HW/SW partitioning and codevelopment. Memory/Register map accurate. Cycle performance estimation. Bit-width and transfer-size constrained data types to allow mapping to bus bursts or fragments of bursts. Split pipeline with time delays. TL1 Detailed analysis and low level SW development. Clock-accurate protocols mapped to the chosen HW interfaces and bus structure. Modeling CA interfaces for abstract simulation models of IP blocks such as embedded processors. Interface pins are hidden. CA performance simulation. Byte-accurate data Transactions have internal structure (protocols, data, clock). Parametrizable to model different bus protocol and signal interfaces. 4 HW/SW/Network design flow Network alternatives TL2 TL1 RTL TL3 TLM refinement TL3 TL2 TL1 TLM/Network refinement RTL 5 V-CLIP: Voice over IP client Voice over IP client IP network 6 V-CLIP: mapping to available tools SystemC (HW/SW) Voice Signal Generator ADPCM Coder RTP/UDP connection RTP Packet Generator NS-2 (network) Linux Workstation Voice player 7 V-CLIP: block diagram 8 Step 1 system: V-CLIP TL3 SystemC SOURCE TL3 Untimed functionality modeling Architecture-abstract implementation Abstract data types RTP High simulation speed! SystemC 2.1 (standard IEEE 1666) Standard OSCI TLM API ADPCM SC-NS interface Network (NS2) 9 Step 1 network ns_sc_agent SystemC RTP voice Actual network 0 10Mb/s Source 2 64kb/s 3 Linear PCM 16000 sample/s, 16 bit/sample --> 256 kb/s After ADPCM compression: 64 kb/s RTP: 1000 byte/packet --> 125ms algorithmic delay 10 Step 2: activation of concurrent traffic ns_sc_agent SystemC RTP voice Actual network 0 10Mb/s 10Mb/s 2 80kb/s 3 1 generic UDP Constant bitrate (CBR) generator 11 Step 3: hw vs. network parameters setting ns_sc_agent SystemC RTP voice Actual network 0 Smaller packets: 10Mb/s 1000 --> 100 byte 12.5 ms delay higher bitrate 2 80 kb/s 3 12 Step 4: V-CLIP TL2 First HW/SW partitioning SOURCE Request FIFO CPU (SW) Response FIFO SystemC RTP TL2 High-level bus channel Non-blocking calls put() request and get() response Decoder Bus arbiter and decoder Event driven simulation Bus Arbiter ADPCM (HW) SC-NS interface Network (NS2) 13 Step 5: V-CLIP TL1 SOURCE Request FIFO Clock-accurate simulation CPU (SW) SystemC RTP Response FIFO Master transactor Decoder TL2 Master transactor AMBA AHB Bus Slave transactor Arbiter Clock-accurate protocols mapped to the chosen HW interfaces and bus structures AMBA Bus Signal level communication with the bus clk TL1 Performance analysis Slave transactor TL2 ADPCM (HW) SC-NS interface Network (NS2) 14 Step 6: V-CLIP TL1/RTL CPU (SW) SOURCE Request FIFO SystemC RTP ADPCM RTL synthesizable Response FIFO Master transactor TL2 Master transactor clk AMBA AHB Bus Slave transactor TL1 Slave transactor TL2 adpcm transactor SC-NS interface Network (NS2) ADPCM RTL clk 15 V-CLIP: overall design flow 16 V-CLIP SystemC/VHDL CPU (SW) SOURCE SystemC SystemC – VHDL co-simulation RTP Request FIFO Response FIFO Master transactor TL2 Master transactor clk AMBA AHB Bus Slave transactor TL1 Slave transactor ModelSim© Mentor Graphics RTL IP-cores reuse TL2 adpcm transactor ADPCM RTL clk sc-ns interface VHDL 17 RTP RTP CPU (SW) TCP/IP TL2 Master transactor TL2 Master transactor TL1 clk TL1 clk Slave transactor Slave transactor TL2 sc_ns_agent interface SystemC CPU (SW) SystemC V-CLIP: sc-ns interfaces NS agent UDP packets TL2 Network (NS2) sc_ns_link interface (Ethernet) Network (NS2) NS node IP packets 18