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Embedded Ethernet Controller
Advanced Embedded Systems Architecture
EE 382N-4
Project Review
Henry Chang
Corey Thacker
5/16/2009
Agenda
• Project Overview
– Work Breakdown
• Hardware Design
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Project Board
Microcontroller Unit Overview
EMAC
Ethernet Physical Transceiver
• Software Design
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System Driver
API
OpenTCP Stack
Application Software
• Demonstration
• Conclusion/Summary
Project Overview
• Goals
– Port TCP IP stack to an embedded microcontroller
– Establish microcontroller on a network
– Communicate with the microcontroller on a network
Project Overview
• TCP IP Stack
– Four layers
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Link
Internet
Transport
Application
– Encapsulation and decapsulation of data for
different communication
services within a network
– Improves reliability of data
traveling from host to host
Assignment
Task
Owner
System Driver
Henry
OpenTCP API
Henry
Embedded Application Henry/Corey
PC Test Application
Corey
Agenda
•
Project Overview
– Work Breakdown
• Hardware Design
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Project Board
Microcontroller Unit Overview
EMAC
Ethernet Physical Transceiver
Software Design
– System Driver
– API
– OpenTCP Stack
– Application Software
Demonstration
Conclusion/Summary
Hardware Design Overview
• Freescale MC9S12NE64 Ethernet Evaluation Board
includes:
– MC9S12NE64 microcontroller
• Provides HW necessary for Ethernet connectivity -- a communications stack, flash
memory, random access memory (RAM), a media access controller (MAC) and
physical layer (PHY) transceiver
– External FLASH and EEPROM memory
– Ethernet connector and a BDM connector
– Other board features include LEDs, a serial
connector, a potentiometer, DIP-switches and pushbuttons
MC9S12NE64 MCU
• Key MC9S12NE64 features:
– 112 pin MCU
– 16-bit HCS12 Core
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HCS12 CPU
Operating frequency – 50 MHz
Memory Map and Interface
Interrupt Control
– Memory – 64 KB FLASH EEPROM and 8KB RAM
– Analog-to-Digital Converter
– Ethernet Media Access Controller (EMAC)
• 802.3 compliant
• Flow control using pause frames
– Ethernet 10/100 Mbps Transceiver (EPHY)
• Half-duplex and Full-duplex
• Available Loop-back modes
– CRG (clock and reset generator module)
• Pierce oscillator
• PLL frequency multiplier
• 25 MHz crystal oscillator reference clock
Ethernet Media Access Controller (EMAC)
• Features:
– IEEE 802.3 compliant supporting 10/100 Ethernet
operation
– Medium-independent interface (MII)
– Full and half duplex modes
– Address recognition
• Unicast, Multicast
• Promiscuous mode
– Loopback mode
– Two receive and one transmit Ethernet buffer
interfaces
– PortE 0 and PortH 4 to 6 is input for Buttons
• 8K RAM as a buffer
– In addition to operating as the CPU storage, the 8K
RAM functions as the EMAC’s Ethernet Buffer
EMAC Block Diagram
Ethernet Physical Transceiver (EPHYV2)
• Features:
– IEEE 802.3 compliant
– Medium-independent interface (MII) supporting data rates of 10 Mbps
and 100 Mbps
• Independent four-bit wide transmit and receive paths
– Auto-negotiation
– Digital Adaptive Equalization
– 125 MHz clock generator and timing recovery
– Single RJ45 connection
– Loopback modes
– Low Power modes – Stop mode, Wait Mode, and MII power down
EPHYV2 Block Diagram
EPHYV2 Sub-Block Diagram
Agenda
•
•
Project Overview
– Work Breakdown
Hardware Design
– Project Board
– Microcontroller Unit Overview
– EMAC
– Ethernet Physical Transceiver
• Software Design
– System Driver
– API
– OpenTCP Stack
– Application Software
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•
Demonstration
Conclusion/Summary
Software Design Overview
System Drivers
• System Clock Initialization
– Choose PLL as clock source
– Set PLL multiply and divide registers
– Core speed is 50Mhz and Bus speed is 25Mhz
• Port Initialization
– PortG 0 to 3 is output for LED
– PortG 4 is input for Switch
– PortE 0 and PortH 4 to 6 is input for Buttons
• ATD Initialization
– 10 bit resolution
– No buffering
– Only read Potentiometer output
System Drivers
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Ethernet Initialization
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Set default IP and MAC addresses
Clear and reset TX and RX buffers
Enable EPHY
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Initialize EMAC
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Setup MII interface speed
Setup Buffer Map
Designate Max packet length (~1500)
Half duplex, no HW flow control, accept all link protocols
Enable all Emac interrupts (TX, RX, Error…)
Configure EPHY via MII interface
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Assign PHY an address
Disable auto negotiate
Allow SW to control LEDs
Temporarily Turn off EPHY PLL
Enable Ephy interrupts
Set half dulplex, and 100Mbps
Turn on EPHY PLL
Real time interrupt
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Setup up interrupt frequency
Enable real time interrupt
API
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Transmit Interface
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Receive Interface
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Write byte
Write word
Write bytes
Initialize Tx Buffer
Start Frame Transmission
Write Ethernet Header to Tx Buffer
Read byte
Read word
Read bytes
Initialize Rx Buffer Offset
Check for valid frame reception
Grab Received Frame
Rx buffering scheme
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Received frames are queued in a double buffer
Frames must be de-queued in order to be removed from the buffer
Incoming frames are dropped if buffer is full
OpenTCP
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Details:
– Description:
• Portable implementation of TCP/IP and Internet application-layer protocols intended for
resource constrained environments (embedded microprocessors)
– Author:
• Jari Lahti
– Company:
• Viola Systems (http://www.violasystems.com)
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List of protocols can be implemented with OpenTCP
– Application Layer
• DHCP Client, SMTP Client, POP3 Client, Http Server, TFTP Server, DNS
– Transport Layer
• UDP, TCP
– Internet Layer
• IP (Version 4), ICMP
– Link Layer
• ARP, Ethernet
Application
Application
• DHCP Client/Server Interface
– Discovery:
• The client broadcast a
message to all DHCP servers
requesting an address
– Offer:
• DHCP server responds
offering the client an IP
address
– Request:
• DHCP client broadcast a
message communicating
which offer it has accepted
– Acknowledge:
• DHCP server who’s offer has
been accepted responds with
an acknowledgement.
Application
• UDP Demo Message Definitions
– Source = MCU, Destination = PC
• b1, b2, b3, b4
– b# = button# pressed
• s0, s1
– s0 = switch off
– s1 = switch on
• data
– ATD data from potentiometer
– data = 0 to 1023 for 10-bit ATD
– Source = PC, Destination = MCU
• l1n, l2n, l3n, l4n
– l#n = led# ON
• l1f, l2f, l3f, l4f
– l#n = led# OFF
Application
• ARP Manage
– If ARP cache table does not contain the HW
address of the remote PC or it is time to
update ARP table.
• ARP request is broadcast on the network
– Example: “Who has 192.168.0.108 tell 192.168.0.140”
• ARP response is broadcast by the owner of the
requested IP address.
– Example: “192.168.0.108 is at 00:0c:f1:44:ed:c6”
Agenda
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Project Overview
– Work Breakdown
Hardware Design
– Project Board
– Microcontroller Unit Overview
– EMAC
– Ethernet Physical Transceiver
Software Design
– System Driver
– API
– OpenTCP Stack
– Application Software
• Demonstration
•
Conclusion/Summary
Demonstration
Agenda
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Project Overview
– Work Breakdown
Hardware Design
– Project Board
– Microcontroller Unit Overview
– EMAC
– Ethernet Physical Transceiver
Software Design
– System Driver
– API
– OpenTCP Stack
– Application Software
Demonstration
• Conclusion/Summary
Conclusion/Summary
• Assumptions
– Turned off auto negotiate to simplify initialization
– Manually set speed to 100 Mbps and Duplex to Half Duplex to avoid
dealing with pause frames.
– Left out error handling interrupts
• Issues
– Ethernet LEDs blinked too quickly when controlled by EPHY, Used SW
too control LEDs instead
– Local MAC address of the stack was reversed
– DHCP server will not offer client IP address if the MAC address starts
with a “01”.
– Timeout setting on the DHCP client was set incorrectly
• Future Plans
– Implement other parts of the stack in the application and verify their
functionality