Download LabLecture6

Good Design & Network Audio
EECS150 Fall2008 - Lab Lecture #6
Chris Fletcher
Adopted from slides designed by
Greg Gibeling and Chris Fletcher
10/3/2008
EECS150 Lab Lecture #6
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Today (1)
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Good Design
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FSMs: The Good, Bad and Ugly
Interfaces (Part 1)
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Signal Conditioning
Administrative Info
EECS150 Lab Lecture #6
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Today (2)
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Lab #6: Network Audio
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Motivation
Network Organization
Ethernet Packets
Eth2Audio
Async FIFO
EECS150 Lab Lecture #6
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Finite State Machines (1)
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After all we have told you…
FSMs seldom lead to efficient circuits
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The Real Story
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When they are not useful
When they are useful
How you can tell between the two cases
EECS150 Lab Lecture #6
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Finite State Machines (2)
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Most FSMs look like…
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Important properties
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Straight path
No complicated branching logic
EECS150 Lab Lecture #6
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Finite State Machines (3)
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It’s a ring counter!
Bubble-Arc diagrams don’t necessitate
the FSM design pattern
EECS150 Lab Lecture #6
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Finite State Machines (4)
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Conclusion
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Think simple
A counter is an incredibly powerful circuit
On the other hand…
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Some FSMs look like…
(await the very necessary page turn)
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EECS150 Lab Lecture #6
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Look any different?
Complex branching!
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EECS150 Lab Lecture #6
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Finite State Machines (6)
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Do not use FSMs when you have…
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Use FSMs when you have…
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Few branches
Linear transitions
Many branches
Complicated decision logic
Conditional transitions
EECS150 Lab Lecture #6
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Signal Conditioning (1)
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Off-by-a-cycle Errors
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Adaptors between complex modules
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Shorten a Pulse
Lengthen a Pulse
Shift a Pulse
Simple modification outside module
Don’t/Can’t touch module internally
EECS150 Lab Lecture #6
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Signal Conditioning (2)
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Shorten a Pulse
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5 Cycles -> 4 Cycles
In
Out
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Any guesses?
What if we delayed the input?
EECS150 Lab Lecture #6
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Signal Conditioning (3)
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Shorten a Pulse
In
In_Delayed
Out
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Out = In & In_Delayed
In_Delayed
In
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Reg
EECS150 Lab Lecture #6
Out
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Signal Conditioning (4)
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Lengthen a Pulse
In
In_Delayed
Out
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Out = In | In_Delayed
In_Delayed
In
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Reg
EECS150 Lab Lecture #6
Out
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Administrative Info
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Project starts next friday: 10/10
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SVN Repositories
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Digital Oscilloscope!
Commit to your partner
The first checkpoint is 1 week long
Will be online at the end of next week
Version-control tutorial on the way
EECS150 Lab Lecture #6
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Lab #6: Network Audio
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Play Audio off Ethernet
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A Major Project by Itself
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Receive Ethernet packets
Decode and remove header
Filter packets
Play audio data payload
Given: Ethernet, Audio, ETC
To be written: Packet Decode & Filtering
EECS150 Lab Lecture #6
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Lab #6: Network Audio
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Your project and Lab 6
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Audio  Ethernet  Waveform
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Stream audio into oscilloscope
Audio Visualizations
EECS150 Lab Lecture #6
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Network Organization (1)
Audio
Stream
TA
Station
WHITE (0)
CaLinx2
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CaLinx2
CaLinx2
CaLinx2
CaLinx2
EECS150 Lab Lecture #6
CaLinx2
CaLinx2
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Network Organization (2)
DO NOT MODIFY
THE PRODUCTION
NETWORK
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EECS150 Lab Lecture #6
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Ethernet Packets (1)
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We’re using raw Ethernet
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Raw Ethernet:
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No TCP/IP, its too complex
Cant use this on the internet
48bit Destination MAC Address
48bit Source MAC Address
16bit Ethernet Type
Payload
32bit CRC
EECS150 Lab Lecture #6
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Ethernet Packets (2)
Ethernet Packet Format
Broadcast Audio Packet
32bits
32bits
Destination [47:16]
0xFFFFFFFF
Source [47:32]
0xFFFF
Source [31:0]
Ethernet Type [15:0]
0x0090
0xc2001c50
Reserved [15:0]
0x0101
0x????
PCM Audio Data Sample 0 [31:0]
PCM Audio Data Sample 0 [31:0]
PCM Audio Data Sample 1023 [31:0]
PCM Audio Data Sample 1023 [31:0]
1024words
1028words
Destination [15:0]
CRC [31:0]
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Ethernet Packets (3)
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A Good Packet
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Total: 1028x 32bit Words
48bit Destination (0xFFFFFFFFFFFF)
48bit Source (0x0090c2001c50)
16bit Packet Type (0x0101)
16bit Padding (0x????)
1024x 32bit PCM Audio Data
EECS150 Lab Lecture #6
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Ethernet Packets (4)
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A Bad Packet
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Who knows how long?
Source and Destination could be anything
Packet Type probably not 0x0101
Coping with bad packets
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Do NOT send them to AudioTop
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Just keep dropping data until end of packet
Done Signal: InPacketValid & InPacketInvalid
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PHY_RX_CLK (~25MHz)
Eth Rx Unit
AP_BIT_CLOCK (12MHz)
Eth2Audio
AC97 Controller
AP_SDATA_IN
Receive Block Diagram
EECS150 Lab Lecture #6
LM4549A
Codec
Output Shift Register
AP_SDATA_OUT
Async
FIFO32
32b PCM Audio Data
Decode &
Filter
32b PCM Audio Data
MAC Rx
Unit
32b Ethernet Packet Data
Input Shift Register
4bit Raw Ethernet Data
Register
LXT975
Ethernet
PHY
4bit Raw Ethernet Data
~25MHz Ethernet Clock
Lab #6: Eth2Audio (1)
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Lab #6: Eth2Audio (2)
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Signal
Width Dir Description
DIn
32
I
Data from MAC_Top
InValid
1
I
Indicates DIn is valid
InPacketValid
1
I
Indicates the end of a good(crc) packet
InPacketInvalid
1
I
Indicates the end of a bad(crc) packet
EthernetClock
1
I
25MHz Ethernet Clock
EthernetReset
1
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EthernetClock sync. Reset
AudioClock
1
I
12.288MHz Audio Clock
AudioReset
1
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AudioClock sync. Reset
DOut
32
O
Data out to AudioTop
OutRequest
1
I
AudioTop requesting a new word
OutValid
1
O
Indicates DOut is valid
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Lab #6: Async FIFO (3)
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Buffer to match two data
rates
Great for data path clock
domain crossings
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Write on one clock (WR_)
Read on another (RD_)
Good place to buffer audio
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Lab #6: Eth2Audio (4)
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Design
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No FSMs allowed
Word Counter
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Valid Register
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Stores whether the packet is valid or not
Reset
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How many bits wide?
When do you reset word counter and valid
register?
EECS150 Lab Lecture #6
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Lab #6: Eth2Audio (5)
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Testing
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We give you a very nice testbench
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Fix your module in simulation
You can use ChipScope w/ 1 clock
Checkoff
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Read Lab5Testbench.v
Read Lab5TestPackets.txt
We should hear nice clean audio
Show us your module using ChipScope
EECS150 Lab Lecture #6
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