Download Switching vs Routing Overview

Switching vs Routing
Presentation

Julia Vuong and Travis Anderson
Switching vs Routing Overview

Switching and Routing are the core functionality of Internetworking

Once physical links are added and clean of errors, resets, and other problems very
little time is spent on physical/data link problems. Wide Area connections have
more link problems but are reliable except for wireless communications.

Most network design and administration issues arise from Switching and Routing
device configuration and implementation.
Switching vs Routing Foundation

Switching

Switching moves traffic
from an input interface to
one or more output
interfaces. Switching is
optimized and has lower
latency than routing
because it can move
packets, frames, or cells
from buffer to buffer with
simpler determination of
the source and destination
of the traffic. It saves
resources because it does
not involve extra lookups.

Routing

Routing is more
processing intensive and
has higher latency than
switching as it determines
path and next hop
considerations. The first
packet routed requires a
lookup in the routing
table to determine the
route. The route cache is
populated after the first
packet is routed by the
route-table lookup.
Subsequent traffic for the
same destination is
switched using the routing
information stored in the
route cache.
Switching Core
A basic switch would be considered a layer two device. When we use the word layer, we
are referring to the 7-layer OSI model.
Switching Core
A switch does not just pass electrical signals along, like a hub does; instead, it
assembles the signals into a frame (layer two), and then decides what to do with the
frame.
A switch determines what to do with a frame by borrowing an algorithm from another
common networking device: a transparent bridge.
Logically, a switch acts just like a transparent bridge would, but it can handle frames
much faster than a transparent bridge could (because of special hardware and
architecture).
Once a switch decides where the frame should be sent, it passes the frame out the
appropriate port (or ports).
You can think of a switch as a device creating instantaneous connections between
various ports, on a frame by frame basis.
Content-Addressable Memory
This example shows the output associated with the Media Access Control (MAC)
address of an Asyncronous Transfer Mode (ATM) dual PHY OC-12 module, which
includes the dynamic CAM entries for all VLANs:
Console> show cam dynamic VLAN Dest MAC/Route Des Destination Ports or VCs
---- ------------------ ---------------------------------------------------00-14-14-14-14-17 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct
6 00-14-14-14-14-14 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-15 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-1a 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-1b 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-18 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-19 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-1c 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 6
00-14-14-14-14-1d 4/1 VCD:98 VPI:0 VCI:127 Type: LANE Data Direct 3
Do you wish to continue y/n [n]? q
Total Matching CAM Entries Displayed = 21
Console>
Transparent Switching Step 1
Step 1—Packet enters the switch
When
a frame enters the switch, the input port takes the frame in and places it in the
input buffer.
The
input buffer is design to handle store-and-forward checking and holding of the
frame, while PINNACLE arbitrates for access onto the switching bus.
There
is a local arbiter on each line card that is responsible for allowing each port on
each PINNACLE access to the switching bus. This local arbiter signals the central
arbiter (on the Supervisor Engine), which is responsible for allowing each local arbiter
to allow frames onto the switching bus.
Transparent Switching Step 2
Step 2—Packet sent across switching fabric and lookup takes place.
This switching bus is on a shared medium, meaning that all the ports on the switch see the packet
as it is on the bus.
Once
the central arbiter has granted access to the switching fabric, the packet is sent across the
bus. All ports begin downloading that packet into their transmit buffers.
The
Policy Feature Card (PFC) is also looking at the switching bus, sees the frame and initiates a
lookup. First, the Layer 2 table is consulted.
If
the packet is local to the Virtual Local Area Network (VLAN), a switching decision is finished.
If
the Layer 2 table is the router’s MAC address, then the Layer 3 Engine examines the packet and
determines if a forwarding entry exists in hardware.
If
If
not, the packet is sent to the Multilayer Switch Feature Card (MSFC).
an entry does exist, the destination VLAN is identified and the Layer 2 lookup table is consulted
again, this time to determine the MAC address within the VLAN and is associated outbound port.
Transparent Switching Algorithm
If
the destination MAC address is found in the CAM table, then the switch will send the
frame out the port that is associated with that destination MAC address in the CAM table.
This is called forwarding.
If the associated port to send the frame out is the same port that the frame originally came
in on, then there is no need to send the frame back out that same port, and the frame is
ignored. This is called filtering.
If the destination MAC address is not in the CAM table (the address is "unknown"), then
the switch will send the frame out all other ports that are in the same VLAN as the received
frame. This is called flooding. It will not flood the frame out the same port on which the
frame was received.
If the destination MAC address of the received frame is the broadcast address
(FFFF.FFFF.FFFF), then the frame is sent out all ports that are in the same VLAN as the
received frame. This is also called flooding. The frame will not be sent out the same port on
which the frame it was received.
Transparent Switching Step 3
Step 3—Forwarding the packet
Now that the outgoing interface has been identified, all the ports on the switch that are not the
destination port are told, over the Results Bus, to flush their buffers of that packet.
The Results Bus also carries to the destination port the MAC re-write information and the
appropriate Quality of Service (QOS) parameters to use (so the packet can be queued correctly on
the outgoing port).
Once the destination port has received the packet, PINNACLE queues the packet in the correct
queue and then uses the SP/WRR scheduler to switch the frame out of memory to the destination
external to the switch.
Transparent Switching Diagram
Routing Step 1
A transit packet entering the Cisco 10000 Series from an interface card is sent over the
backplane by the interface card.
When it reaches the Performance Routing Engine (PRE), the packet is stored in buffer
memory internal to the backplane interface ASIC.
Routing Step 2
The backplane interface ASIC then passes the packet header to the Parrallel Express
Forwarding (PXF) pipeline, which classifies the packet, modifies the packet
header, and may modify the packet data.
As part of this processing, the PXF selects the output interface on which to forward the
packet.
Routing Algorithm
The place to start our discussion of IP routing is to understand what is maintained by
the kernel in its routing table. The information contained in the routing table
drives all the routing decisions made by IP.
Steps that IP performs when it searches its routing table.
1.
Search for a matching host address.
2.
Search for a matching network address.
3.
Search for a default entry. (The default entry is normally specified in the routing
table as a network entry, with a network ID of 0.)
A matching host address is always used before a matching network address.
The routing done by IP, when it searches the routing table and decides which interface
to send a packet out, is a routing mechanism. This differs from a routing policy,
which is a set of rules that decides which routes go into the routing table. IP
performs the routing mechanism while a routing daemon normally provides the
routing policy.
Routing Step 3
In the simplest packet-routing cases, the PXF then commands the backplane interface
ASIC to store the packet in the backplane interface ASIC packet-buffer memory,
in one of possibly several software output queues associated with the output
interface.
Subsequently, the PXF output scheduling function applies various algorithms on these
output queues to select which packet to send next.
When a packet is scheduled for actual transmission on the output interface, PXF
directs the backplane interface application-specific integrated circuit (ASIC) to
copy the packet to the hardware queue associated with the output interface.
The backplane interface ASIC will then transfer the packet across the backplane, and
the packet will be sent on the output link by the line-card hardware.
Routing Diagram
Routing a Packet
Making Forwarding Decisions
router#show ip route ....
D 192.168.32.0/26 [90/25789217] via 10.1.1.1
R 192.168.32.0/24 [120/4] via 10.1.1.2
O 192.168.32.0/19 [110/229840] via 10.1.1.3 ....
If a packet arrives on a router interface destined for 192.168.32.1, which route would the
router choose? It depends on the prefix length, or the number of bits set in the
subnet mask. Longer prefixes are always preferred over shorter ones when
forwarding a packet.
In this case, a packet destined to 192.168.32.1 is directed toward 10.1.1.1, because
192.126.32.1 falls within the 192.168.32.0/26 network (192.168.32.0 through
192.168.32.63). It also falls within the other two routes available, but the
192.162.32.0/26 has the longest prefix within the routing table (26 bits verses 24 or
19 bits).
Likewise, if a packet destined for 192.168.32.100 arrives on one of the router's interfaces,
it's forwarded to 10.1.1.2, because 192.168.32.100 doesn't fall within 192.168.32.0/26
(192.168.32.0 through 192.168.32.63), but it does fall within the 192.168.32.0/24
destination (192.168.32.0 through 192.168.32.255). Again, it also falls into the range
covered by 192.168.32.0/19, but 192.168.32.0/24 has a longer prefix length.
Cisco Express Forwarding
Functionality
Functional Description
Cisco Express Forwarding (CEF) is advanced
Layer 3 IP switching technology. CEF
optimizes network performance and
scalability for networks with large and
dynamic traffic patterns, such as the Internet,
on networks characterized by intensiveWebbased applications, or interactive sessions.
Cisco Express Forwarding
CEF Components
Information conventionally stored in a route cache is stored in several data structures
for CEF switching. The data structures provide optimized lookup for efficient
packet forwarding. The two main components of CEF operation are the
• Forwarding Information Base
• Adjacency Tables
Forwarding Information Base
Forwarding Information Base
CEF uses a Forwarding Information Base (FIB) to make IP destination prefix-based switching
decisions.
The FIB is conceptually similar to a routing table or information base. It maintains a mirror image
of the forwarding information contained in the IP routing table.
When routing or topology changes occur in the network, the IP routing table is updated, and those
changes are reflected in the FIB.
The FIB maintains next-hop address information based on the information in the IP routing table.
Because there is a one-to-one correlation between FIB entries and routing table entries, the FIB
contains all known routes and eliminates the need for route cache maintenance that is
associated with earlier switching paths such as fast switching and optimum switching.
Adjacency Tables
Adjacency Tables
Network nodes in the network are said to be adjacent if they can reach each other with
a single hop across a link layer.
In addition to the FIB, CEF uses adjacency tables to prepend Layer 2 addressing
information.
The adjacency table maintains Layer 2 next-hop addresses for all FIB entries.
Distributed CEF
Distributed CEF Mode
When distributed CEF (dCEF) is enabled, line cards, such as Versatile Interface
Processor (VIP) line cards or Gigabit Switch Router (GSR) line cards, maintain
an identical copy of the FIB and adjacency tables. The line cards perform the
express forwarding between port adapters, relieving the Route Switch Processor
(RSP) of involvement in the switching operation. dCEF uses an Inter Process
Communication (IPC) mechanism to ensure synchronization of FIBs and
adjacency tables on the route processor and line cards. Figure 3 shows the
relationship between the route processor and line cards when dCEF mode is
active.
Figure 3 dCEF Mode
In this Cisco 12000 series router the line cards perform the switching. In other routers
where you can mix various types of cards in the same router, it is possible that
not all of the cards you are using support CEF. When a line card that does not
support CEF receives a packet, the line card forwards the packet to the next
higher switching layer (the route processor) or forwards the packet to the next
hop for processing. This structure allows legacy interface processors to exist in
the router with newer interface processors
DCEF Diagram
References
www.cisco.com
www.nortel.com
www.redback.com
www.extremenetworks.com
www.nokia.com
www.marconi.com
Questions
1. What are the 3 functions of Switching?
A. forwarding
B. filtering
C. flooding
D. All of the above.
Answer: D. All of the above
2. What steps does IP perform when when it searches its routing table?
A. Search for a matching host address.
B. Search for a matching network address.
C. Search for a default entry.
D. All of the above.
Answer: D. All of the above.