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Ethernet Bomber Ethernet Packet Generator for network analysis Final Presentation Oren Novitzky & Rony Setter Advisor: Mony Orbach Started: Spring 2008 Project Goals Developing a hardware Ethernet packet generator for Ethernet networks benchmarking. Support stand-alone operation with several user configurations. Implementation of the system on Altera PCI-E Development kit board with Stratix II GX FPGA. Project Goals Learning common communication protocols such as Ethernet, UDP, IP Learning HW development language and tools. Building SW application to support and control the HW design. Architecture guideline: Hardware Optimization: - Accelerating the NIOS by implement large instruction/ data cache. - Using high speed external memory – DDR2 - Interfacing Altera’s TSE MAC with SGDMA (instead of NIOS II directly) - Increasing core clock from 100MHz to 166.67MHz using only one PLL. Architecture guideline: Software Optimization: - Using the UDP protocol (instead of TCP) to increase throughput performance - Networking with InterNiche’s “NicheStack” fully configurable networking stack and MicroC/OS-II operating system. - Raising compiler optimization level to maximum (3). Block Diagram NIOS II terminal JTAG PHY Marvell Ethernet MAC MII Altera TSE On chip Memory RJ-45 SGDMA Interface UDP/IP Packet generator NicheStack UDP Nios II Networking External Ethernet 10/100 Mbps Ext. CLK 100MHz JTAG Debug Module DDR2 HP Controller + PLL @ 333MHz DDR2 SDRAM Flash HP Controller Flash memory SOPC Architecture DDR2 Memory Controller S On-chip Memory JTAG UART NiosII JTAG Processor Debug Module S Data M Inst M S System Timer S S Avalon Main BUS (HS) Pipeline Bridge (LS) S S SGDMA TX Src Avalon Tristate S SGDMA RX M Sink S Sink Src Triple speed Ethernet MAC S Simple I/O Controllers S FLASH Memory Controller SOPC Architecture Software Design Overview The application code is based on a template supplied by Altera for networking application designs (Simple Socket Server template). The TSE device driver is also supplied by Altera and needs to be integrated to the software build in Nios II EDS library configuration. Both the IP layer and the device driver are supplied by InterNiche Technologies. Using third party WireShark 1.2.5 Network Protocol Analyzer (freeware) at the receiver station. Software Structure – Thread Level Lower number = Higher priority Program main() benchmark_initial_task() Priority 1 tk_netmain() tk_nettick() benchmark_driver() Priority 2 Priority 3 Priority 4 NicheStack Tasks Benchmarking Application Task Software Structure – Code Level main() nios_get_command_string() benchmark_initial_task() bmcommand_from_console() bmprint_menu() alt_iniche_init() legal command? netmain() iniche_net_ready NO YES print_test() NO benchmark() udp_sender_plain() YES bmprint_start() udp_sender() benchmark_driver() socket() sendto() gettimeofday() Delay? YES Calling Flow waiting done? NO NO Sending done? YES YES print_result() NO System Setup Benchmarking Example - Transmitter Benchmarking Example - Receiver Benchmarking Example - Results Benchmarking Example - Results Benchmarking Example - Results Benchmarking Example - Results Conclusion Networking Performance As published by Altera and InterNiche, reaching maximum link speed using this integrated design is doable, without the need of implementing the IP layer in HW. Altera design suit and documentation Although Altera’s documentation resources are almost endless, more than once we encountered mismatch between several documents (Quartus/NIOS/SOPC) Future designs on this hardware platform Our hardware platform consists of all the required features for future fast networking standalone designs