Download EE 545 Summer 1999 - RIT - People

EE 482 — Electronics II
Lab #2: Common-Emitter Amplifier Design
Overview
The objective of this lab is to design, simulate, and verify the performance of a common-emitter
amplifier.
Background
A common-emitter amplifier is a widely used voltage amplifier due to its high gain and its
reasonable tolerance to variations in transistor parameters. A discrete design for the commonemitter amplifier is shown in Figure 1. A voltage divider comprised of resistors R1 and R2 is used to
set the DC bias voltage at the base of the BJT. Figure 1 shows VCC as 15 V, but the circuit that you
design and build could have a somewhat different supply voltage. (In an integrated circuit design, a
current source would be used in place of some of the resistors shown in Figure 1; additionally, the
current source could function as an active load.)
Figure 1. Common-Emitter Amplifier Schematic
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 1 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
Pre-Lab
Review the planned experiments and record relevant background information and equations that
will be used for design of the common emitter amplifier. Design and simulate the amplifier to meet
the design specifications assigned by the TAs. A suggested design approach is given below.
Each group will be randomly given two design specifications by the TAs:
(1) a minimum value for magnitude of voltage gain: 20 22 24 26 28 30 [V/V] (  10%); and,
(2) a power supply voltage value: 14 15 16 [V].
The required minimum output swing specification (peak-to-peak amplitude) is 5 V less than your
supply voltage. For example, if your supply voltage is 14 V, your output voltage must be able to
swing  4.5 V, for a total peak-to-peak output swing of 14 – 5 = 9 V.
Each group must design the amplifier by selection of R1, R2, RC, Re1 and Re2 using standard 5%
tolerance resistor values (no parallel/series resistor combinations are allowed). Use 100 μF
capacitors for C1-C3. All circuits must be simulated prior to building the circuit in lab, including a
Monte Carlo analysis (see Appendix for procedure) using standard 5% resistors to demonstrate
robustness to variation in the design. The 3904 npn BJT can be found by searching for the
Q2N3904 part. Load resistance is constant at 3.3 k.
In DC analysis, assume VBE = 0.7 V. Use the β calculated in the Lab #1 (BJT characterization) and
design for a DC collector current of 6 mA.
Sample design approach (you may need to iterate to your final design, but this can provide a
starting point):
1. Choose VCC/4 < VB < VCC/2
2. Set I1=10*IB  Calculate R1
3. Set I2=9*IB  Calculate R2
4. Set (Re1 + Re2) to get IC.
5. Set RC to meet the output voltage swing specification (remember to consider both VCC
supply and transistor saturation).
6. Use small signal gain to determine Re1.
7. Round calculated resistor values to standard 5% tolerance values, then analyze the
resulting design to verify that it meets the design specifications.
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 2 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
Lab Exercise
Build the circuit of Figure 1 using your designed resistor values. Use a signal frequency of 10 kHz,
and an initial amplitude of 100 mV to measure your voltage gain. You will likely need to increase
the amplitude of the input signal in order to confirm that you can accommodate the required amount
of voltage swing at the output. For example, if you had a target peak-to-peak swing of 9 V at the
output and a measured voltage gain magnitude of 30 V/V, you would need an input signal of 9/30 V
= 300 mV peak-to-peak, or 150 mV amplitude in order to drive the output with the target amount of
swing.
Tech Memo Analysis


Summarize your design calculations, as well as the re-analysis of your design after rounding
calculated resistor values to standard 5% tolerance values.
Compare hardware results to simulated results. Discuss any discrepancies.
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 3 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
Appendix: Monte Carlo Analysis (Orcad 9.2 Lite Edition)
Background
Monte Carlo analysis allows us to evaluate the impact of component tolerances and other
non-idealities on circuit performance. Following are instructions on how to perform a successful
Monte Carlo simulation.
1. Adding Tolerances to Resistors
a. Double-click the resistor symbol to which you wish to add tolerance.
b. In the “Filter by” pull-down menu select “Orcad-Pspice”.
c. At the far right end of the table, under the tolerance label, enter the desired tolerance
value in percentage format (i.e., 10%).
d. Click “Apply” in the upper left-hand corner to activate the value entered.
e. Close the properties window.
2. Setup Simulation Profile
a. For a new simulation:
i. Hit “New Simulation Profile” icon,
.
ii. Input a profile, leave the “Inherited from” empty.
iii. Follow “For existing profile” steps from here on.
b. For existing profile:
i.
ii.
iii.
iv.
v.
vi.
vii.
viii.
ix.
x.
xi.
xii.
Hit “Edit Simulation Settings” icon,
.
Simulation Settings window will pop up.
Choose “Time domain (transient)” under Analysis type.
Input proper time interval for “Run to time” (i.e., about 1 period).
Select “Monte Carlo/Worst Case” in Options.
Type in the name for “Output variable” (i.e., V(RL:2)).
Input “Number of runs” (usually given).
Type any number between 1 and 32767 into the “Random number seed” box.
Click “More Settings” button on the lower right-hand corner.
Choose “the maximum value (MAX)” from the pull-down menu.
Click Apply.
Hit OK, then OK again.
(cont’d)
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 4 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
3. Running Capture CIS
a. Hit the blue “Run Pspice” button on the tool bar
simulation should be running at this time]
. [Pspice window will pop up and
b. Hit OK to close the window that pops up.
c. The graph will then pop up with the voltage you wanted, provided you placed a voltage
probe in the circuit.
d. If it’s blank it is because you did not place a probe in the circuit. You can do so at this
time and the corresponding voltage curve should appear immediately on the graph.
4. How to Get a Performance Analysis Layout (Histogram)
a. In the top menu, click on “Trace” and then “Performance Analysis”.
b. In the window that pops up, click on the “Wizard” button at the bottom.
c. Click NEXT.
d. Select “Max” from the list and click NEXT.
e. In the text box, type in the same thing you put in the “Output Variable” for the Monte
Carlo profile (i.e., V(RL:2)).
Click FINISH and you should see the performance analysis above the graph.
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 5 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
(This page intentionally left blank)
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 6 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922
Check-Off Sheet
TA Signature: ____________________________ Date: ___________________________
Electronics II – EE 482 — Lab #2: Common-Emitter Amplifier Design — Rev 1.3 (6/8/09)
Page 7 of 7
Rochester Institute of Technology
Teaching Assistants — Office: 09-3248; Phone: x5-70922