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Electronics for RICH Detectors
Veljko Radeka, BNL
RICH 2004 Workshop
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche
gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
1
Acknowledgements:
•
•
•
•
•
•
Gianluigi De Geronimo
Paul O’Connor
Sergio Rescia
Pavel Rehak
Craig Woody
Bo Yu
… my BNL colleagues.
2
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche
gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
3
CMOS Technology Roadmap
Year
199
1
1993
1995
Min. feature size
[nm]
800
500
350 250 180 130 90
60
Oxide thickness
[nm]
16
11
7.7
5.5
4
2.7
2.2
1.8
Power supply [V]
5
5/3.3
3.3
2.5
1.8
1.5
1.2
0.9
Threshold
voltage [V]
0.7
0.65
0.6
0.5
0.38
0.28
0.22
0.17
Cutoff frequency
[GHz]
12
19
28
40
65
75
100
165
•
•
1997
1999
Driven by digital VLSI circuit needs
Goals: in each generation
– 2X increase in density
– 1.5X increase in speed
2001
2004
2008
4
CMOS scaling:
Oxide Thickness:
10
100
Volts
kT/q
tox /d Si
Supply voltage
5
Threshold voltage
0
0.25
0.18
0.15
0.13
Lmin, m
0.1
0.07
10
0.25
0.18
0.15
0.13
Lmin, m
0.1
5
0.07
Threshold mismatch due to
discrete dopant distribution
3D p-MOSFET simulation with
stochastically placed dopants
D.J. Frank, IBM J. Res. Dev. 46, 235-244, Mar./May 2002
DVT
Dopant atoms per MOSFET
1000
500
0
0.25
0.18
0.15
0.13
Lmin, m
0.1
0.07
6
But:
Gate tunneling current
!!!
• Gate current expected to
increase 100 – 200 x per
generation below 0.18 mm
• Jox ~ 100 A/cm2 projected for Lmin
= 0.1 mm generation with
nitrided SiO2
• Considered tolerable for digital
circuits (total gate area per chip
~ 0.1 cm2)
• Typical CSA input FET would
have IG ~ 1 - 10 µA; ENCp ~
2000 - 7000 rms e- at 1 µsec
• Good for radiation resistance
– bad for ENC.
SiO2 gate leakage current (Lo et al., Electron
Dev. Letters 1997)
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FPGAs - Thirteen Years of Progress
200x More Logic
plus memory, µP,
DSP, MGT
40x Faster
50x Lower Power
per function x MHz
500x Lower Cost
per function
P. Alfke
8 LHC Boston Sept 04 PA
Higher Leakage Current…
High Leakage current = static power consumption
Was <100 microamps, now > 100 mA, even amps (!)
Caused by:
Gate leakage due to 16 Å gate thickness
Sub-threshold leakage current
incomplete turn-off because threshold does not scale
Tyranny of numbers:
10 nA x 100 million transistors = 1 A
evenly distributed, thus no reliability problem
Sub-100 nm is not ideal for portable designs
P. Alfke
9 LHC Boston Sept 04 PA
VLSI ASIC Costs ….
Mask set >$1M + design + verification + risk
Source:IBM
P. Alfke
10 LHC Boston Sept 04 PA
Custom monolithics: technology access
Multiproject foundry services
• Combine designs from many
institutions on one maskset
• Arrange for regular runs with a
variety of popular foundries
• Design support
• Models
• Design rules
– Process monitoring
• Amortize cost of run over many
users
multiproject wafer
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Front-End Electronics – Preamplifier Power
Energy Resolution [ENC]
400
TECHNOLOGY SUPPLY COST/RUN
0.35µm
3.3V
14k$
0.25µm
2.5V
19k$
0.18µm
1.8V
32k$
300
200
100
0.01
0.1
1
Preamplifier Power [mW]
 32-channel ASIC - layout is pad-limited  3 x 3 mm²
 power / channel  1mW (preamplifier < 200µW)
 energy resolution < 250 rms electrons (600ns peaking time, 5pF)
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Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche
gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
13
14
Single Electron Detection and Timing vs Avalanche
Gain Gav
Detection (Yes/No):
Gav ≥ ~ 10 ENC/qe
“Common” Timing:
Gav ≥ (ENC/qe) (tp/σt) ;
tp = peaking time after shaping
> signal current width
Optimum timing:
---------------------------------------1. Coarse timing: ~ 1 – 2 ns ,
for tp = 20ns
→ Gav ≥ 10 ENC/qe
= 100 ns →
≥ 50 ENC/qe
2. Precision timing: ~ 100 – 200 ps , for tp = 20 ns → Gav ≥ 100 ENC/qe
ENC = ?
(Note: Optimum filter for timing is different from opt. filter for charge measurement)
15
Optimum ENC vs Input Capacitance
TSMC 0.25µm
P-MOS, Tp=20ns
ENCopt [r.m.s. electrons]
1000
Pd=100µW
Pd=1mW
100
Pd=10µW
10
10
-14
10 fF
10
-13
10
-12
Input capacitance Cin [F]
10
-11
10 pF
Power Pd is in input leg only. Add minimum 30µW for signal processing
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Optimum ENC vs Input Capacitance
1000
ENCopt [r.m.s. electrons]
TSMC 0.25µm
P-MOS, Tp=200ns
Pd=100µW
100
Pd=1mW
Pd=10µW
10
1
-14
10
10 fF
10
-13
10
-12
Input capacitance Cin [F]
10
-11
10 pF
Power Pd is in input leg only. Add minimum 30µW for signal processing
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“Why is the detector capacitance so important in
determining the noise performance?”
It is illustrative to express the noise performance in terms of signal and noise “energy” on the
detector capacitance. From matched filter theory and the well known relations for ENC:
for white series noise
for 1/f series noise
=transistor carrier transit time ≈ Cgs/gm ; tm= integration time ; Kf is the 1/f noise
constant [Joules]; kB= Boltzmann constant.
Numerical (dimensionless) constants aw , a1/f ,
contain capacitance matching constraints (Cd/Cgs ratio), weighting function shape
parameters, but are independent of the transistor width.
Amplifier noise energy referred to the detector capacitance is independent of the
detector capacitance. The signal energy is inversely proportional to the detector
capacitance.
(Cd here includes stray capacitances.)
For a “gut feeling”: Charge at higher potential energy is easier to detect – 1 electron on
1 atofarad (quantum dot) is readily detectable – while not so at higher capacitances.
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VR 06/17/04
Pixel density – detector trends
1E+6
1E+7
LSST
1E+6
1E+5
barcode
1E+5
DEPFET1
M'pix2
DEPFET2
1E+4
XAMPS1
1E+3
LHC pixels
1E+3
1E+2
1E+2
EXAFS
PHX MVD
PET
1E+1
gamma cam
1E+1
STAR TPC
1E+0
Doubling every 5 months
1E+0
PHX PAD
1E-1
AP
S
M
PE
T
2006
LS
ST
XA
M
PS
1
ba
rc
od
e
LH
C
pi
xe
ls
DE
PF
ET
2
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m
m
EX
AF
S
m
2002 Year 2004
ca
'pi
x2
ga
DE
PF
ET
1
2000
M
PA
D
PH
X
PH
X
TP
C
1998
M
VD
1E-1
1E-2
ST
AR
pixels/cm2
1E+4
MAPS
2008
2010
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Power density
• On-detector power
density is limited by
cooling capability.
• Electronics for highdensity detector must
be extremely low
power.
20
Silicon sensor (for EXAFS spectroscopy)
sample
sensor
• 384 pixels
• 1 x 1 x 0.25 mm Si pad detector
• rate > 10 MHz/cm2
• 8.2 mW/chan
• FWHM < 300eV, noise < 28 e• preamps + digital integrated on-chip
G. De Geronimo et al., Proc. PIXEL2002 International Workshop, Carmel, CA, 2002
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Optimized noise vs. power
(MOSFET optimized at each power level and shaping time)
Shaping
time:
Noise (rms e-)
1000
10 ns
30
100
300
1000
3000
100
Note:
dN
 0 .4
dP
d ln N
 0.4
d ln P
10
10
100
1000
10000
Power (W)
Cd = 1pF
0.25 µm CMOS
22
G. DE Geronimo, P. O`Connor
Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche
gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
23
Detector – FE interconnect choices
• board-to-backplane
–
–
–
–
easy to test, repair
large boards possible
connector pins are failure points
coarse pitch and high capacitance (> 1pF)
• standard SMT package soldered to board (QFP or BGA)
–
–
–
easy to test, difficult to repair
capacitance down to 0.2 pF for small packages
board area limited by reflow oven capacity
• wirebonded chip-on-board
–
–
–
–
difficult to test, assemble, and repair
board area limited by wirebonder
fragile
low capacitance (0.1 pF)
• bump-bonded flip-chip
–
–
–
can match pixels with pitch from ~30 – 1000 m
difficult to test, assemble, and repair
circuitry has to fit in same area as pixel
• monolithic detector/electronics
–
–
interconnect is created as part of the detector
fabrication process
ultra-low capacitance (few fF)
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Interpolating Pad Readout for GEM (Gas Electron Multiplier)
<100µm
rms
position
resolution
with 2mm
pad pitch
Window
Upper GEM
Lower GEM
Anode Pad
Plane
25
Time Projection Chamber (TPC) – (for Laser Electron Gamma Source)
TPC Can
double-GEM
planes
HV mesh plane
and UV window for
laser calibration
anode pad plane
electronics per pad
~ 8000 channels
Spin ASYmmetry Array (SASY)
26
Board layout for a
TPC – GEM anode
plane.
32 channels per
ASIC.
~ 8000 channels →
~ 10 watts on 35
cm dia plane
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Board layout for a
TPC – GEM anode
plane.
ASICS
Blind vias
GEM foils
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ASIC Layout
buffer
channel
 TSMC 0.25µm
 32 channels
 3.1 x 3.6 mm² (~0.35
mm2/channel)
 47k MOSFETs
 43mW
 QFN package (56)
bias
logic
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ASIC Readout Channel - Block Diagram
neighbors
flag
continuous reset
threshold
2nd order
shaper
CONTINUOUS RESET
• feedback MOSFET
• self adaptive
• low noise
• fully compensated
• US patent 5,793,254
• NIM A421, p.322
• TNS 47, p.1458
 350 µW
mux1
PD
timing
detector
mux2
TD
baseline
stabilizer
ramp
INPUT n-MOSFET
• optimized for operating region
• ENC<250 rms electrons
• NIM A480, p.713
peak
detector
SHAPER
• amplifier with passive feedback
• dual stage multiple feedback
• 2nd order, 600ns peaking time
• adjustable channel gain (3-bit)
BASELINE STABILIZER (BLH)
• band-gap referenced
• low-frequency feedback
• slew-rate limited follower
• high dc stability < 1mV
• low channel dispersion < 4mV
• TNS 47, p.818
PEAK DETECTOR
• two-phase configuration
• offset error cancellation
• high absolute accuracy < 0.2%
• US patent 6,512,399
• NIM A484, p.544
TIMING DETECTOR
• time-to-amplitude converter
• internal or external ramp
• two-phase configuration
• timing resolution < 20ns rms
 900 µW
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Electronics for RICH Detectors
• Developments in electronics: CMOS scaling
• The quest for single electron sensitivity: avalanche
gain vs electronic noise and detector capacitance
• A neglected technology: Interconnections
• Matching electronics and detector technology
32
GEM Readout of the
HBD
• Triple GEM
- can be made insensitive to charged
particles
- minimizes photon feedback and ion
backflow
• Modest gain (~ 5 x 103)
• CsI photocathode deposited on top
surface of uppermost GEM foil
Prototype HBD detector
• CF4 used as working gas and
Cherenkov
radiator
- can achieve high gain and good
transmission down into deep VUV
( large N0)
33
Readout Board and Preamps
Preamp signals to
shaper + ADC
Hybrid Preamps
with line drivers
• Being developed by
BNL Instrumentation
~ ¾”
honeycomb
• Based on IO-535
wires
Read pads
~ 3x3 cm2
•± input signal
•± 2.5 V output
GEMs
• Need almost one full rack for the readout electronics
34
The HBD Detector
HBD Gas Volume: Filled
with CF4 Radiator
(nCF4=1.000620, LRADIATOR = 50 cm)
Proximity focused
Cherenkov
forms “blobs”
on an image
plane
(Qmax = cos-1(1/n)~36
mrad rBLOB~3.6cm)
Coarse granularity
readout (~ 2x2 cm2)
Windowless Cherenkov Detector
Radiator gas = Working Gas
e+
e-
q
Pair Opening
Angle
Triple GEM
detectors
Dilepton pair
(8 panels per side)
Electron pairs
produce Cherenkov
light, but hadrons
with P < 4 GeV/c do
not
55 cm
5 cm
Beam Pipe
Space allocated
for services
35
Low-Noise preamplifier – thick film
ceramic hybrid
• single channel
• 29 components
• 44 solder joints
• 8 connections to PCB
• 20 x 14 x 2.5 mm
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Highly segmented detectors
N=1
N=9
N=25
Benefits:
• Position Resolution
– pixel pitch ~ 1/N
• Energy resolution (ENC)
– CDET ~ 1/N
– IDARK ~ 1/N
– pulse shaping time ~ N
• Rate capability
– pileup ~ 1/N
• “Small pixel” effect
– improve energy resolution in
semiconductor detectors with poor
hole transport
N=49
Drawbacks:
• Interconnect density
→ bump bonding; BGAs
~N
• Electronics channel count ~ N
But these are not “old channels”!
•
Power/channel
~1/N
Noise is reduced more due to lower C,
than increased due to lower power.
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Concluding remarks:
• Microelectronics technology allows us to take
advantage of fine electrode segmentation
• This leads to lower noise and lower avalanche gain
• Tough luck to very large electrode pads – not well
matched to microelectronics
• Detector, detector electrodes, interconnections and
the ASIC are all constituents of an interactive design.
• Scaling of digital electronics (powerful FPGAs)
allows real time processing close to or on detector
39
ASIC Designer vs the Rest of the Collaboration
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