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Chapter 2
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Chapter 2
2.1 Introduction
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•
Language of the Machine
We’ll be working with the MIPS instruction set architecture
– similar to other architectures developed since the 1980's
– Almost 100 million MIPS processors manufactured in 2002
1400
– used by NEC,
Nintendo,
Cisco, Silicon Graphics, Sony, …
Other
1300
1200
1100
1000
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
900
IA-32
800
ARM
700
600
500
400
300
200
100
0
1998
1999
2000
2001
2002
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2.2 Operations of the Computer Hardware
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All instructions have 3 operands
Operand order is fixed (destination first)
Example:
C code: a = b + c
MIPS ‘code’: add a, b, c
#the sum of b and c is placed in a.
(we’ll talk about registers in a bit)
“The natural number of operands for an operation like addition is
three…requiring every instruction to have exactly three operands, no
more and no less, conforms to the philosophy of keeping the
hardware simple”
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MIPS arithmetic
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Design Principle: simplicity favors regularity.
Of course this complicates some things...
C code:
a = b + c + d + e;
MIPS code:
add a, b, c
add a, a, d
add a, a, e
Example:
C code:
MIPS code:
a = b + c;
d = a - e;
add a, b, c
sub d, a, e
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Example:
C code:
f = (g + h) – (i + j);
MIPS code:
add t0, g, h
add t1, i, j
sub f, t0, t1
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2.3 Operands of the Computer Hardware
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Operands of arithmetic instructions must be registers, only 32 registers provided
Each register contains 32 bits
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Design Principle: smaller is faster.
Why?
Example: Compiling a C Assignment using registers
f = (g + h) – (i + j)
variables f, g, h, I and j are assigned to registers: $s0, $s1, $s2, $s3, and $s4 respectively
MIPS Code:
add $t0, $s1, $s2
add $t1, $s3, $s4
sub $s0, $t0, $t1
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Memory Operands
Data Transfer instructions
• Arithmetic instructions operands must be registers,
— only 32 registers provided
• Compiler associates variables with registers
• What about programs with lots of variables
Control
Input
Memory
Datapath
Processor
Output
I/O
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Memory Organization
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Viewed as a large, single-dimension array, with an address.
A memory address is an index into the array
"Byte addressing" means that the index points to a byte of memory.
0
1
2
3
4
5
6
...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
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Example:
g = h + A[8];
Where
g  $s1
h  $s2
base address of A  $s3
MIPS Code:
lw $t0, 8($s3) # error
add $s1, $s2, $t0
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Hardware Software Interface
Alignment restriction
• Bytes are nice, but most data items use larger "words"
• For MIPS, a word is 32 bits or 4 bytes.
0
4
8
12
...
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•
•
32 bits of data
32 bits of data
32 bits of data
Registers hold 32 bits of data
32 bits of data
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
Words are aligned
i.e., what are the least 2 significant bits of a word address?
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Instructions
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Load and store instructions
Example:
C code:
A[12] = h + A[8];
where: h  $s2
base address of A  $s3
MIPS code:
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•
•
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 48($s3)
Can refer to registers by name (e.g., $s2, $t2) instead of number
Store word has destination last
Remember arithmetic operands are registers, not memory!
Can’t write:
add 48($s3), $s2, 32($s3)
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Constant or Immediate Operands
Constant in memory:
lw $t0, AddrConstant4($s1)
add $s3, $s3, $t0
#$t0 = constant 4
#$s3 = $s3 + $t0
Constant operand (add immediate):
addi $s3, $s3, 4
#$s3 = $s3 + 4
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So far we’ve learned:
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MIPS
— loading words but addressing bytes
— arithmetic on registers only
•
Instruction
Meaning
add $s1, $s2, $s3
sub $s1, $s2, $s3
lw $s1, 100($s2)
sw $s1, 100($s2)
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
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2.4 Representing Instructions in the Computer
• Instructions, like registers and words of data, are also 32 bits long
Example: add $t0, $s1, $s2
– registers have numbers, $t0=8, $s1=17, $s2=18
Instruction Format (MIPS Fields):
000000 10001
op
6 bits
op:
rs:
rt:
rd:
shamt:
funct:
rs
5 bits
10010
01000
00000
100000
rt
5 bits
rd
5 bits
shamt
5 bits
funct
6 bits
opcode.
first register source
second register source
register destination
shift amount
function code
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R-format and I-format
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Consider the load-word and store-word instructions,
– What would the regularity principle have us do?
– New principle: Good design demands a compromise
Introduce a new type of instruction format
– I-type for data transfer instructions
– other format was R-type for register
Example: lw $t0, 32($s2)
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18
8
op
rs
rt
6 bits
•
5 bits
5 bits
32
constant or address
16 bits
Where's the compromise?
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Translating MIPS Assembly into Machine Language
Example:
A[300] = h + A[300];
$s2 $t1
is compiled into:
lw $t0, 1200($t1)
add $t0, $s2, $t0
sw $t0, 1200($t1)
---------t0  8
t1  9
s2  18
100011
01001
01000
000000
10010
01000
101011
01001
01000
0000 0100 1011 0000
01000
00000
100000
0000 0100 1011 0000
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So far we’ve learned:
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Stored Program Concept
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Instructions are bits
Programs are stored in memory
— to be read or written just like data
memory for data, programs,
compilers, editors, etc.
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Fetch & Execute Cycle
– Instructions are fetched and put into a special register
– Bits in the register "control" the subsequent actions
– Fetch the “next” instruction and continue
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2.5 Logical Operations
Example:
sll
$t2, $s0, 4
# reg $t2 = reg $s0 << 4 bits
$s0 contained:
0000 0000 0000 0000 0000 0000 0000 1001
After executions:
0000 0000 0000 0000 0000 0000 1001 0000
Op
Rs
Rt
Rd
shamt
funct
0
0
16
$s0
10
$t2
4
0
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Logical opeartions: and or nor
$t1:
$t2:
$t1 & $t2
$t1 | $t2
0000
0000
0000
0000
$t1:
$t3:
~($t1 | $t3)
0000 0000 0000 0000 0011 1100 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000
1111 1111 1111 1111 1100 0011 1111 1111
and $t0, $t1, $t2
or $t0, $t1, $t2
nor $t0, $t1, $t3
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0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0011
0000
0000
0011
1100
1101
1100
1101
0000
0000
0000
0000
0000
0000
0000
0000
# $t0 = $t1 & $t2
# $t0 = $t1 | $t2
# $t0 = ~($t1 | $t3)
andi: and immediate
ori : or immediate
No immediate version for NOR (its main use is to invert the bits of a single
operand.
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So far we’ve learned:
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2.6 Instruction for Making Decisions
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Decision making instructions
– alter the control flow,
– i.e., change the "next" instruction to be executed
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MIPS conditional branch instructions:
beq $t0, $t1, Label
bne $t0, $t1, Label
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Example:
if (i==j) h = i + j;
i$s0
i$s1
h$s3
bne $s0, $s1, Label
add $s3, $s0, $s1
Label: ....
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If-else
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MIPS unconditional branch instructions:
j label
Example:
f ≡s0 g ≡s1 h ≡s2 i ≡s3 and j ≡s4
if (i==j)
f=g+h;
else
f=g-h;
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bne $s3, $s4, Else
add $s0, $s1, $s2
j Exit
Else: sub $s0, $s1, $s2
Exit: ...
Can you build a simple for loop?
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loops
Example: Compiling a while loop in C:
While (save[i] == k)
i += 1;
Assume: i ≡s3
k ≡s5 base-of A[]≡s6
Loop:
sll
add
lw
bne
add
j
$t1, $s3, 2
$t1, $t1, $s6
$$t0, 0($t1)
$t0, $$5, Exit
$s3, $s3, 1
loop
Exit:
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So far:
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Instruction
Meaning
add $s1,$s2,$s3
sub $s1,$s2,$s3
lw $s1,100($s2)
sw $s1,100($s2)
bne $s4,$s5,L
beq $s4,$s5,L
j Label
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Next instr. is at Label if $s4 ≠ $s5
Next instr. is at Label if $s4 = $s5
Next instr. is at Label
Formats:
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
funct
26 bit address
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Continue
set on less than instruction:
slt $t0, $s3, $s4
slti $t0, $s2, 10
Means:
if($s3<$s4) $t0=1;
else $t0=0;
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2.7 Supporting Procedures in Computer Hardware
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$a0-$a3:
$v0-Sv1:
$ra:
jal:
jr $ra:
four arguments
two value registers in which to return values
one return address register
jump and save return address in $ra.
jump to the address stored in register $ra.
Using More Registers
• Spill registers to memory
• Stack
• $sp
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Example: Leaf procedure
int leaf_example(int g, int h, int i, int j)
{
int f;
f=(g+h)-(i+j);
return f;
}
leaf_example:
addi $sp, $sp, -12
sw $t1, 8($sp)
sw $t0, 4($sp)
sw $s0, 0($sp)
add
add
sub
add
$t0,
$t1,
$s0,
$v0,
$a0,
$a2,
$t0,
$s0,
$a1
$a3
$t1
$zero
lw $s0, 0($sp)
lw $t0, 4($sp)
lw $t1, 8($sp)
addi $sp, $sp, 12
jr $ra
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Nested Procedures
int fact (int n)
{
if(n<1) return (1);
else return (n*fact(n-1));
}
fact:
addi $sp, $sp, -8
sw $ra, 4($sp)
sw $a0, 0($sp)
slti $t0, $a0, 1
beq $t0, $zero, L1
addi $v0, $zero, 1
addi $sp, $sp, 8
jr $ra
L1: addi $a0, $a0, -1
jal fact
lw $a0, 0($sp)
lw $ra, 4($sp)
addi $sp, $sp, 8
mul $v0, $a0, $v0
jr $ra
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Allocating Space for New Data on the Stack
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Stack is also used to store Local variables that do not fit in registers
(arrays or structures)
Procedure frame (activation record)
Frame Pointer
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Allocating Space for New Data on the Heap
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Need space for static variables and dynamic data structures (heap).
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Policy of Use Conventions
Name Register number
$zero
0
$v0-$v1
2-3
$a0-$a3
4-7
$t0-$t7
8-15
$s0-$s7
16-23
$t8-$t9
24-25
$gp
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$sp
29
$fp
30
$ra
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Usage
the constant value 0
values for results and expression evaluation
arguments
temporaries
saved
more temporaries
global pointer
stack pointer
frame pointer
return address
Register 1 ($at) reserved for assembler, 26-27 for operating system
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2.8 Communicating with People
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For text process, MIPS provides instructions to move bytes (8 bits ASCII):
lb $t0, 0($sp)
Load a byte from memory, placing it in the rightmost 8 bits of a register.
sb $t0, 0($gp)
Store byte (rightmost 8 bits of a register) in to memory.
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Java uses Unicode for characters: 16 bits to represent characters:
lh $t0, 0($sp) #Read halfword (16 bits) from source
sh $t0, 0($gp) #Write halfword (16 bits) to destination
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Example:
void strcpy(char x[], char
y[])
{
int i;
i=0;
while((x[i]=y[i])!=‘\0’)
i+=1;
}
strcpy:
addi $sp, $sp, -4
sw
add
L1: add
lb
add
sb
beq
addi
j
L2: lw
addi
jr
$s0,
$s0,
$t1,
$t2,
$t3,
$t2,
$t2,
$s0,
L1
$s0,
$sp,
$ra
0($sp)
$zero, $zero
$s0, $a1
0($t1)
$s0, $a0
0($t3)
$zero, L2
$s0, 1
0($sp)
$sp, 4
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2.9 MIPS Addressing for 32-Bit Immediates and Address
32-Bit Immediate Operands
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load upper immediate lui to set the upper 16 bits of a constant in a register.
lui $t0, 255 # $t0 is register 8:
001111
00000
01000
0000 0000 1111 1111
Contents of register $t0 after executing: lui $t0, 255
0000 0000 1111 1111
0000 0000 0000 0000
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Example: loading a 32-Bit Constant
What is the MIPS assembly code to load this 32-bit constant into register $s0
0000 0000 0011 1101 0000 1001 0000 0000
lui $s0, 61
The value of $s0 afterward is:
0000 0000 0011 1101 0000 0000 0000 0000
ori $s0, $s0, 2304
The final value in register $s0 is the desire value:
0000 0000 0011 1101 0000 1001 0000 0000
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Addressing in Branches and Jumps
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jump addressing
j
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10000
#go to location 10000
2
10000
6 bits
26 bits
Unlike the jump, the conditional branch must specify two operands:
bne $s0, $s1, Exit # go to Exit if $s0 ≠ $s1
5
16
17
Exit
6 bits
5 bits
5 bits
16 bits
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No program could be bigger than 216, which is far too small
Solution: PC-relative addressing
Program counter = PC + Branch address
PC points to the next instruction to be executed.
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Examples:
Showing Branch Offset in Machine Language
loop:
while (save[i] == k)
i += 1;
sll $t1, $s3, 2
add $t1, $t1, $s6
lw $t0, 0($t1)
bne $t0, $s5, Exit
addi $s3, $s3, 1
j Loop
Exit:
80000
0
0
19
9
2
0
80004
0
9
22
9
0
32
80008
35
9
8
0
80012
5
8
21
2
80016
8
19
19
1
80020
2
80024
………
2000
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Example
Branching Far Away
Given a branch on register $s0 being equal to $s1,
beq $S0, $s1, L1
replace it by a pair of instructions that offers a much greater branching distance.
These instructions replace the short-address conditional branch:
bne $s0, $s1, L2
j
L1
L2: ...
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MIPS Addressing Modes Summary
1. Immediate addressing
op
1.
2.
3.
4.
5.
Register addressing
Base or displacement
addressing
Immediate addressing
PC-relative addressing
Pseudodirect addressing: 26
bits concatenated with the upper
bits of the PC.
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
+
Register
Byte
Halfword
Word
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
+
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
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Decoding Machine Language
What is the assembly language corresponding to this machine code:
00af8020hex
0000 0000 1010 1111 1000 0000 0010 0000
From fig 2.25, it is an R-format instruction
000000
00101
01111
10000
00000
100000
from fig 2.25, Represent an add instruction
add $s0, $a1, $t7
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Constants
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Small constants are used quite frequently (50% of operands)
e.g.,
A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?
– put 'typical constants' in memory and load them.
– create hard-wired registers (like $zero) for constants like one.
MIPS Instructions:
addi $29, $29, 4
slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
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Design Principle: Make the common case fast.
Which format?
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How about larger constants?
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We'd like to be able to load a 32 bit constant into a register
Must use two instructions, new "load upper immediate" instruction
lui $t0, 1010101010101010
1010101010101010
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filled with zeros
0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
ori
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Assembly Language vs. Machine Language
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Assembly provides convenient symbolic representation
– much easier than writing down numbers
– e.g., destination first
Machine language is the underlying reality
– e.g., destination is no longer first
Assembly can provide 'pseudoinstructions'
– e.g., “move $t0, $t1” exists only in Assembly
– would be implemented using “add $t0,$t1,$zero”
When considering performance you should count real instructions
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Other Issues
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Discussed in your assembly language programming lab:
support for procedures
linkers, loaders, memory layout
stacks, frames, recursion
manipulating strings and pointers
interrupts and exceptions
system calls and conventions
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Some of these we'll talk more about later
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We’ll talk about compiler optimizations when we hit chapter 4.
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Overview of MIPS
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simple instructions all 32 bits wide
very structured, no unnecessary baggage
only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
funct
26 bit address
rely on compiler to achieve performance
— what are the compiler's goals?
help compiler where we can
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Addresses in Branches and Jumps
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Instructions:
bne $t4,$t5,Label
$t5
beq $t4,$t5,Label
$t5
j Label
op
I
Formats:
op
J
rs
Next instruction is at Label if $t4 °
Next instruction is at Label if $t4 =
Next instruction is at Label
rt
16 bit address
26 bit address
Addresses are not 32 bits
— How do we handle this with load and store instructions?
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Addresses in Branches
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Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
Formats:
I
•
•
Next instruction is at Label if $t4≠$t5
Next instruction is at Label if $t4=$t5
op
rs
rt
16 bit address
Could specify a register (like lw and sw) and add it to address
– use Instruction Address Register (PC = program counter)
– most branches are local (principle of locality)
Jump instructions just use high order bits of PC
– address boundaries of 256 MB
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To summarize:
MIPS operands
Name
32 registers
Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
$a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero always equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
2
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Accessed only by data transfer instructions. MIPS uses byte addresses, so
memory Memory[4], ...,
words
and spilled registers, such as those saved on procedure calls.
add
MIPS assembly language
Example
Meaning
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
Used to add constants
Category
Arithmetic
sequential words differ by 4. Memory holds data structures, such as arrays,
Memory[4294967292]
Instruction
addi $s1, $s2, 100
lw $s1, 100($s2)
sw $s1, 100($s2)
store word
lb $s1, 100($s2)
load byte
sb $s1, 100($s2)
store byte
load upper immediate lui $s1, 100
add immediate
load word
Data transfer
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register
Word from register to memory
Byte from memory to register
Byte from register to memory
Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
set less than
immediate
slti
jump
j
jr
jal
jump register
jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500
$ra
2500
Jump to target address
go to 10000
For switch, procedure return
go to $ra
$ra = PC + 4; go to 10000 For procedure call
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1. Immediate addressing
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Register
3. Base addressing
op
rs
rt
Memory
Address
+
Register
Byte
Halfword
Word
4. PC-relative addressing
op
rs
rt
Memory
Address
PC
+
Word
5. Pseudodirect addressing
op
Address
PC
Memory
Word
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Alternative Architectures
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Design alternative:
– provide more powerful operations
– goal is to reduce number of instructions executed
– danger is a slower cycle time and/or a higher CPI
–“The path toward operation complexity is thus fraught with peril.
To avoid these problems, designers have moved toward simpler
instructions”
•
Let’s look (briefly) at IA-32
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IA - 32
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1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: 57 new “MMX” instructions are added, Pentium II
1999: The Pentium III added another 70 instructions (SSE)
2001: Another 144 instructions (SSE2)
2003: AMD extends the architecture to increase address space to 64 bits,
widens all registers to 64 bits and other changes (AMD64)
2004: Intel capitulates and embraces AMD64 (calls it EM64T) and adds
more media extensions
“This history illustrates the impact of the “golden handcuffs” of compatibility
“adding new features as someone might add clothing to a packed bag”
“an architecture that is difficult to explain and impossible to love”
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IA-32 Overview
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Complexity:
– Instructions from 1 to 17 bytes long
– one operand must act as both a source and destination
– one operand can come from memory
– complex addressing modes
e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:
– the most frequently used instructions are not too difficult to
build
– compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity,
making it beautiful from the right perspective”
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IA-32 Registers and Data Addressing
•
Registers in the 32-bit subset that originated with 80386
Name
Use
31
0
EAX
GPR 0
ECX
GPR 1
EDX
GPR 2
EBX
GPR 3
ESP
GPR 4
EBP
GPR 5
ESI
GPR 6
EDI
GPR 7
EIP
EFLAGS
CS
Code segment pointer
SS
Stack segment pointer (top of stack)
DS
Data segment pointer 0
ES
Data segment pointer 1
FS
Data segment pointer 2
GS
Data segment pointer 3
Instruction pointer (PC)
Condition codes
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IA-32 Register Restrictions
•
Registers are not “general purpose” – note the restrictions below
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IA-32 Typical Instructions
•
Four major types of integer instructions:
– Data movement including move, push, pop
– Arithmetic and logical (destination register or memory)
– Control flow (use of condition codes / flags )
– String instructions, including string move and string compare
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IA-32 instruction Formats
•
Typical formats: (notice the different lengths)
a. JE EIP + displacement
4
4
8
Condi- Displacement
tion
JE
b. CALL
8
32
CALL
Offset
c. MOV
6
MOV
EBX, [EDI + 45]
1 1
8
d w
r/m
Postbyte
8
Displacement
d. PUSH ESI
5
3
PUSH
Reg
e. ADD EAX, #6765
4
3 1
32
ADD Reg w
f. TEST EDX, #42
7
1
TEST
w
Immediate
8
32
Postbyte
Immediate
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Summary
•
•
•
Instruction complexity is only one variable
– lower instruction count vs. higher CPI / lower clock rate
Design Principles:
– simplicity favors regularity
– smaller is faster
– good design demands compromise
– make the common case fast
Instruction set architecture
– a very important abstraction indeed!
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