Download Lecture 3 - BRAC University

CSE 341 – Microprocessors
Lecture 3
Md. Omar Faruqe
[email protected]
http://faculty.bracu.ac.bd/~faruqe
UB 1228
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Execution of Instructions
• Execution of instructions of an Assembly program is sequential unless you
use and instruction such as Jmp.
• The PC (Program Counter) present in a microprocessor holds the memory
location of the next instruction that is to be executed.
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• Now in some cases we would like to perform operation when an external
event takes place.
• There are two ways of monitoring this switch press
• Polling
• Interrupt
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Polling
• The processor checks to see if the external event has occurred at specific
intervals.
• Algorithm for polling:
1. Read P1.0
2. Is P1.0 equals to 0 ( The switch has been pressed?)
a.
b.
c.
d.
Perform some external operation
..........................................
.................................
..................................
3. Go to Step 1
• What is the problem with this type of checking ?
 Your Processors is BUSY/Tied up in the loop
 You may actually miss the external even if not checked at the right
time.
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Interrupts
• The processor is automatically notified that an event has occurred.
• Think of the example of a phone:
• If your phone were on silent and you were expecting a call you would
be checking at intervals to check for the call.
• On the other hand, if your phone has a ring tone than you could be
doing anything and your phone would interrupt you and let you know
that someone was calling you.
• The processor is automatically notified that an event has occurred.
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Interrupts Occur
• The processor completes the current instruction its executing
• Saves the address of the next instruction on top of a Stack
• Jumps to a special location called the Interrupt Vector Table.
• The Interrupt Vector Table contains the address of the ISR (Interrupt
Service Routine)
• There will be a specified ISR to handle each interrupt that they processor
will come across.
• The ISR deals with the interrupt and takes the necessary actions as
defined by the programmer. Once the ISR has been completed the
processor returns to the execution of the original program.
• It does so by retrieving the instruction address which it saved on the top
of the stack. Assembly programs use RETI to specify the return from
Interrupt
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Interrupts & Priority
• Suppose you were on the Phone and the Door Bell rings. What do you do ?
 Ignore the Door and be on the phone
 Hang up and answer the door.
This is your personal preference.
• Microprocessors don’t have preferences, we need to set it for them. This is
known as priority.
• Suppose a microprocessor does three things.
 Sends and receives data
 Updates the display on a LED clock
 Detects FIRE using a smoke alarm
• What should it do if the three events occur at the same time ?
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Interrupts & Priority
• Interrupts are a very important feature of microprocessors and modern
O/S are built based on this ability of µP to use interrupts.
• On a µP there are generally two types of interrupts:
• External – Hardware based. Detected through electrical signals of
special pins of the µP.
• Internal o Timer-Based
o Serial Communication (We will not be dealing with this).
• The 8051 has two pins that act can be used to detect external interrupts.
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Interrupt Structure of 8051
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Port 3
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Interrupt Priority
• By default all the external and internal interrupts are disabled.
• The programmer needs to enable interrupts within the program according
to needs.
• The activation and set up of interrupts requires manipulation of some
SFRs.
• 8051 interrupt priority:
 External Interrupt [INT0]
 Timer 0
 External Interrupt [INT1]
 Timer 1
 Serial Port
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Interrupt Vector Addresses
• So you program is stored in memory locations 30H onwards.
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Program Memory
Locations
User
00
Boot strap / Microprocessor
reads during start-up
03 -29
Reserved Interrupt Vector
Addresses
30 Onwards
Your Program
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Setup for Interrupts
• A SFR called IE (Interrupt Enable) is used to activate interrupts.
• IE is a 8 bit register and can be found at memory location A8
• Each of the 8 bits are allocated to the various interrupts and the register is
bit addressable.
• Being bit addressable each of the bits can be modified separately or
directly.
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IE Structure
• EA – Enable All acts as a switch.
• It either turns ON/OFF all the interrupts of the µP .
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Enable Interrupt INT0
SETB EX0
or
SETB A8H
Disable Interrupt INT0
CLRB EX0
or
CLRB A8H
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Setting Up Interrupts
• Other then IE there are SFRs that need to be set.
• Two more SFRs are needed to set up Interrupts:
 TCON – Timer Control
 IP – Interrupt Priority
NOTE: To use interrupts correctly on 8051 three SFRs need to be initialised and
set correctly.
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TCON
TF1: Timer 1 Overflow Flag
TR1: Timer 1 Run Control Flag
IE1: External Interrupt
It is set to 1 by the processor when a high-to-low edge is received
on the external interrupt pin INT1. It is cleared to zero when the
processor vectors to ISR [ address:0013H].
IT1: External Interrupt 1 Signal Type Control Flag
It may be set to 1 by the program to enable external interrupt 1 to be triggered
by a floating edge signal. It is set to 0 by the program to enable Low-Level signal
triggering on external interrupt INT1.
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IP
PS: Serial Port Priority: Set / Cleared by the program
PT1: Priority of timer 1 overflow: Set / Cleared by the program
PX1: Priority of external interrupt 1: Set / Cleared by the program
PT0: Priority of timer 0 overflow: Set / Cleared by the program
PX0: Priority of external interrupt 0: Set / Cleared by the program
Priority may be 1 for the highest or 0 for lowest.
In the 8051 only the highest and the lowest may be defined
The other interrupts will use the default priority
If the priorities are set incorrectly the processor will revert to default values.
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Exercise
Write an Assembly program for the 8051 to toggle the light when the switch is pressed.
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Hint
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Context Switching
The programmer must ensure that ISR leaves the registers in the same
state as they were before.
For 8051 the programmer must save contents of the following:
 PSW
 DPTR
 Register A (Acc)
 Register B
 Registers 00-07
How do you think this can be achieved ?
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Context Switching
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