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240-334 Computer System Design Lecture 2 Instruction Set Architecture 240-334 by Wannarat What’re the component of ISA? Machine Instruction Set Instruction format Nature of the fetch through execute narat: hine instruction set :make use of storage cells, formats, and result of fetch/execute , register transfer uction format : size and meaning of field within instruction nature of the fetch-execute cycle : things that are done before the operation code is known. 240-334 by Wannarat Varies Programming Model 240-334 by Wannarat What must an instruction specify? Which Operation is perform? ADD r1,r2,r3 Where to find the operands ADD r1,r2,r3 Place to store the result ADD r1,r2,r3 Location of next instruction 240-334 by Wannarat wannarat: Basic ISA Class add A, B ; A = A + B add A B C; A = B + C Accumulator (1 register) 1 address add A; acc <= acc + mem[A] 1 + x address addx A; acc <= acc + mem[A+x] Stack : 0 address add tos <= tos + next General Purpose Register 2 address add A, B 3 address add A, B, C 240-334 by Wannarat Basic ISA Classes(con’t) Load/Store load Ra, Rb Store Ra, Rb Ra <= mem[Rb] mem[Rb] <= Ra 240-334 by Wannarat Compare number of instruction Stack Push A Push B Add Pop C Code Sequence for C = A + B Accumulator Register Register (reg. - mem) (load/store) Load A Add B Store C Load R1,A Add R1,B Store C, R1 240-334 by Wannarat Load R1,A Load R2,B Add R3,R1,R2 Store C,R3 CPU Register Stack Register Arithmetic Register & Address Register 240-334 by Wannarat nnarat: General Purpose Register er for compiler to use : (A*B) - (C*D) - (E*F) can do multiplies in any order vs. stack d variables: memory traffic is reduced (program speed up), code density improves ( register named w er bits than memory location) 1975 - 1995 all machines use general purpose registers. Advanced of Registers - faster than memory - easier for compiler to use - hold variables 240-334 by Wannarat Summary Instruction Set Class Data Movement Instructions - Load - Store Arithmetic and Logic (ALU) Instruction - Add, Sub, Shift … Branch Instructions - Br, Brz, … 240-334 by Wannarat wannarat: 3-Address Machine and ISA Address of next instruction kept in Processor state register (PC) 240-334 by Wannarat 2-Address Machine ISA 240-334 by Wannarat 1-Address Machine and ISA 240-334 by Wannarat 0-Address Machine and ISA k in CPU, stack for both operands and result, have 1-address instruction to push and pop operands to and 240-334 by Wannarat Examples a = (b+c)*d - e 3-address add a,b,c mpy a,a,d sub a,a,e 2-address load a,b add a,c mpy a,d sub a,e 1-address load b add c mpy d sub e store a 240-334 by Wannarat stack push b push c add push d mpy push e sub pop a Real Machine Have mixture of 3, 2, 1 or 0 address instructions if ALU instructions only use registers for operands and result, machine type is load-store mix of register-memory and memory-memory 240-334 by Wannarat Break 5 Minutes 240-334 by Wannarat Addressing Mode 240-334 by Wannarat Addressing Mode Addressing Mode Examples Meaning Register Add r4,r3 r4 <= r4 + r3 Immediate Add r4,#3 r4 <= r4 + 3 Displacement Add r4,100(r1)r4 <= r4 + mem[100+r1] indirect(r) Add r4,(r1) r4 <= r4 + mem[r1] index+base Add r3,(r1+r2) r3 <= r3 + mem[r1+r2] Direct Add r1,(1001) r1 <= r1 + mem[1001] indirect(m) Add r1,@(r3) r1 <= r1 + mem[mem[r3]] auto-incre Add r1,(r2)+ r1 <= r1+mem[r2];r2=r2+d auto-decre Add r1,-(r2) r2 <=r2-d,r1<=r1+mem[r2] scaledAdd r1,100(r2)[r3] r1 240-334 <=r1+mem[100+r2+r3*d] by Wannarat MIPS Registers 31 x 32-bit GPR (R0 = 0) 32 x 32-bit FP register PC lo hi-multiplier output register R0 R1 PC lo hi R31 240-334 by Wannarat Memory Addressing Since 1980, Most machine uses address to level of 8-bits (byte) How do byte address map onto words? Can a word be placed on any byte boundary? 240-334 by Wannarat Endianess and Alignment Big Endian : 68k, SPARC, MIPS, HP PA Little Endian : 80x86,DEC(Vax, Alpha) 240-334 by Wannarat Generic of Instruction format width Variable : ... Fixed: Hybrid : 240-334 by Wannarat Summary ISA Variable length instructions, if code size is very important. Fixed length instructions, if performance is most important. Embedded Machine (ARM, MIPS) have optional mode to execute 16-bit wide. (decide performance or density) 240-334 by Wannarat To be Continuous 240-334 by Wannarat Part II : Lecture 2 240-334 by Wannarat MIPS ISA Target Embedded System used by NEC, Nintendo, Silicon Graphics, Sony 240-334 by Wannarat MIPS ISA 240-334 by Wannarat MIPS Addressing Modes All instructions have 32-bit wide. 240-334 by Wannarat MIPS Arithmetic Instruction Instruction 1.add 2.subtract 3.add imme 4.add unsign 5. 6. 7.multiply 8. Example add $1,$2,$3 sub $1,$2,$3 addi $1,$2,100 addu $1,$2,$3 subu $1,$2,$3 addiu $1,$2,100 mult $2,$3 multu $2,$3 240-334 by Wannarat Meaning $1 = $2 + $3 ------------------------------------------------------------------------------------Hi,Lo = $2x$3 ------------------ MIPS Arithmetic Instruction Instruction 9.divide Example div $2,$3 Meaning Lo=$2/$3, Hi=$2mod$3, 10. 11.mov 12. Divu $2,$3 mfhi $1 mflo $1 240-334 by Wannarat MIPS Logical Instruction Instruction Example Meaning 13.AND and 14.OR or 15.XOR xor 16.NOR nor 17. andi 18. ori 19. xori 20.shift left logical sll $1,$2,10 21. Srl $1,$2,10 240-334 by Wannarat MIPS Logical Instruction Instruction Example 22.shift right arithm sra $,$2,10 23. sllv 24. srlv 25. srav 240-334 by Wannarat Meaning (sign extend) MIPS data transfer instructions 26. 27. 28. 29. 30. 31. 32 sw 500(r4),r3 sh 502(r4),r3 sb 41(r4,r3 lw r1,30(r2) Lh r1,40(r2) Lb r1,40(r2) lui r1,40 load Store word store half word store byte load word load half word load byte upper immediate (16 bits shifted left by 16) 240-334 by Wannarat Testing Condition Condition Code add r1,r2,r3 bz label Condition Register cmp r1,r2,r3 bgt r1,label Compare and Branch bgt r1,r2,label 240-334 by Wannarat MIPS Compare and Branch Compare and Branch BEQ rs,rt,offset BNE rs,rt,offset compare to zero and Branch BLEZ BGTZ BLT BGEZ BLTZAL rs, offset rs, offset < >= if R[rs] < 0 then branch and link(to R31) BGEZAL >= 240-334 by Wannarat MIPS Jump, Branch Compare 240-334 by Wannarat Software conventions for Register 240-334 by Wannarat Note for MIPS Instruction Set R0 always = “0” (even if u try to write) Branch/jump and link PC+4 ->R31 Imme arith and logical are extended - logical imme op are zero extend to 32 bits - arith imme op are sign extend to 32 bits data loaded by lb, lh extended - lbu, lhu are zero extended - lb, lh are sign extedned Overflow occur in ADD, SUB, ADDI Don’t occur in ADDU, SUBU, ADDIU, AND, OR, XOR, NOR, SHIFT, MULT, MULTU, DIV, DIVU 240-334 by Wannarat MIPS arithmetic Instruction has 3 operands Operand order is fixed Pascal Code : a := b + c; MIPS Code : add $s0, $s1, $s2 240-334 by Wannarat MIPS Arithmetic Pascal Code : MIPS Code : a := b + c + d; e := f - a; add $t0, $s1, $s2 add $s0, $t0, $s3 sub $s4, $s5, $s0 240-334 by Wannarat Register & Memory Registers were used in Arithmetic Instructions - 32 registers 240-334 by Wannarat Memory Organization Memory is an index into the array Byte Addressing = points to a byte of memory 1 2 3 4 5 6 7 8 bits of Data 8 bits of Data 8 bits of Data 8 bits of Data 8 bits of Data 8 bits of Data 8 bits of Data 240-334 by Wannarat Memory Organization For MIPS, a word is 32-bit or 4 bytes 232 bytes with byte addresses from 0 to 232-1 230 words with byte address from 0, 4, 32 bits of Data 6, …,232-4 0 32 bits of Data 4 32 bits of Data 8 12 32 bits of Data 16 32 bits of Data 20 32 bits of Data 24 32 bits of Data 240-334 by Wannarat MIPS Load/Store Instruction Code : A[8] = h + A[8]; A[8] ==> 8 x 4 = 32 (word alignment) MIPS Code : lw $t0, 32($s3); add $t0,$s2,$t0; sw $t0, 32($s3); Arithmetic Operand is Register, not Memory!! 240-334 by Wannarat Example : Swap (int v[], int k); { Int temp; temp = v[k]; v[k] = v[k+1]; v[k+1]=temp; } swap: muli $2, $5, 4 add $2,$4,$2 lw $15, 0[$2] lw $16, 4[$2] sw $16, 0[$2] sw $15, 4[$2] jr $31 240-334 by Wannarat Meaning add $2, $4, $2 lw $16, 0[$2] sw $15, 4[$2] $2 = $4 + $2; $16 = Memory[0 + $2] Memory[4+$2] = $15 240-334 by Wannarat Machine Language Instructions, like register & words of data are 32 bits long. - add $t0, $s1, $s2 - register : $t0 = 9, $s1 = 17, $s2 = 18 Instruction Format 240-334 by Wannarat Machine Language I-type for Data transfer instruction Example : lw $t0, 32($s2) 240-334 by Wannarat Control Decision Making instructions MIPS conditional branch instructions: - bne $t0, $t1, label - beq $t0, $t1, label Example : if (i=j) h= i +j; bne $s0, $s1, Label add $s3, $s0, $s1 Label : ... 240-334 by Wannarat Control MIPS unconditional Branch Example : if ( i != j) beq $s4, $s5, label; h=i+j; add $s3, $s4, $s5; else j lab2 h=i-j; lab1: sub $s3, $s4, $s5 lab2: … 240-334 by Wannarat Summarize : 240-334 by Wannarat 240-334 by Wannarat Homework Use MIPS Assembly to write program. 1. “Factorial Program” n is input, Example : if n=3, result = 3! = 3 x 2 x 1 = 6 240-334 by Wannarat Homework Use MIPS Assembly to write program. 2. Write program that use Most of the MIPS instructions 240-334 by Wannarat MIPS Instruction Encoding Please see more detail in the Figure 3.18 Page 153, 240-334 by Wannarat