Download Slide 1

ECE3055
Computer Architecture and
Operating Systems
Lecture 3 MIPS ISA
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Institute of Technology
1
Instructions:
 Language of the Machine
 More primitive than higher level languages
e.g., no sophisticated control flow
 Very restrictive
e.g., MIPS Arithmetic Instructions
 We’ll be working with the MIPS instruction set architecture (some of
you have done this in 2030)
 a representative of Reduced Instruction Set Computer (RISC)
 similar to other architectures developed since the 1980's
 used by NEC, Nintendo, Silicon Graphics, Sony
Design goals: Maximize performance and Minimize cost, Reduce design time
2
MIPS arithmetic
 All instructions have 3 operands
 Operand order is fixed (destination first)
Example:
C code:
A = B + C
MIPS code:
add $s0, $s1, $s2
(associated with variables by compiler)
3
MIPS arithmetic
 Design Principle: simplicity favors regularity.
 Of course this complicates some things...
C code:
A = B + C + D;
E = F - A;
MIPS code:
add $t0, $s1, $s2
add $s0, $t0, $s3
sub $s4, $s5, $s0
 Operands must be registers, only 32 registers provided
 All memory accesses are accomplished via loads and stores

A common feature of RISC processors
4
Registers vs. Memory
 Arithmetic instructions operands must be registers,
— only 32 registers provided
 Compiler associates variables with registers
 What about programs with lots of variables
Control
Input
Memory
Datapath
Processor
Output
I/O
5
Memory Organization
 Viewed as a large, single-dimension array, with an
address.
 A memory address is an index into the array
 "Byte addressing" means that the index points to a
byte of memory.
0
1
2
3
4
5
6
...
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
8 bits of data
6
Memory Organization



Bytes are nice, but most data items use larger "words“
MIPS provides lw/lh/lb and sw/sh/sb instructions
For MIPS, a word is 32 bits or 4 bytes.




(Intel’s word=16 bits and double word or dword=32bits)
0 32 bits of data
4 32 bits of data
Registers hold 32 bits of data
8 32 bits of data
12 32 bits of data
232 bytes...with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
Words are aligned
i.e., what are the least 2 significant bits of a word address?
7
Endianness [defined by Danny Cohen 1981]
 Byte ordering  How a multiple byte data word stored
in memory
 Endianness (from Gulliver’s Travels)
 Big Endian
 Most significant byte of a multi-byte word is stored at the lowest
memory address
 e.g. Sun Sparc, PowerPC
 Little Endian
 Least significant byte of a multi-byte word is stored at the lowest
memory address
 e.g. Intel x86
 Some embedded & DSP processors would support
both for interoperability
8
Example of Endian

Store 0x87654321 at address 0x0000, byte-addressable
0x0000
0x87
0x0001
0x65
0x0002
0x0003
Lower
Memory
Address
0x0000
0x21
0x0001
0x43
0x43
0x0002
0x65
0x21
0x0003
0x87
Higher
Memory
Address
BIG ENDIAN
Lower
Memory
Address
Higher
Memory
Address
LITTLE ENDIAN
9
Instructions
 Load and store instructions
 Example:
4 bytes
A[0]
32 bits of data
A[1]
C code:
MIPS code:
long A[100];
A[2]
A[9] = h + A[8];
lw $t0, 32($s3)
add $t0, $s2, $t0
sw $t0, 36($s3)
32 bits of data
32 bits of data
32 bits of data
 Store word has destination last
 Remember arithmetic operands are registers, not memory!
10
Our First Example
swap(int v[], int k);
{
int temp;
temp = v[k]
v[k] = v[k+1];
v[k+1] = temp;
}
swap:
muli
add
lw
lw
sw
sw
jr
$2, $5, 4
$2, $4, $2
$15, 0($2)
$16, 4($2)
$16, 0($2)
$15, 4($2)
$31
 MIPS Software Convention

$4, $5, $6, $7 are used for passing arguments
11
So far we’ve learned:
 MIPS
— loading words but addressing bytes
— arithmetic on registers only
 Instruction
add $s1, $s2, $s3
sub $s1, $s2, $s3
lw $s1, 100($s2)
sw $s1, 100($s2)
Meaning
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
12
Software Conventions for MIPS Registers
Register
Names
Usage by Software Convention
$0
$zero
$1
$at
$2 - $3
$v0 - $v1
Function return result registers
$4 - $7
$a0 - $a3
Function passing argument value registers
$8 - $15
$t0 - $t7
Temporary registers, caller saved
$16 - $23
$s0 - $s7
Saved registers, callee saved
$24 - $25
$t8 - $t9
Temporary registers, caller saved
$26 - $27
$k0 - $k1
Reserved for OS kernel
$28
$gp
Global pointer
$29
$sp
Stack pointer
$30
$fp
Frame pointer
$31
$ra
Return address (pushed by call instruction)
$hi
$hi
High result register (remainder/div, high word/mult)
$lo
$lo
Low result register (quotient/div, low word/mult)
Hardwired to zero
Reserved by assembler
13
Instruction Format


Instruction
Meaning
add $s1,$s2,$s3
sub $s1,$s2,$s3
lw $s1,100($s2)
sw $s1,100($s2)
bne $s4,$s5,Label
beq $s4,$s5,Label
j Label
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Next instr. is at Label if $s4  $s5
Next instr. is at Label if $s4 = $s5
Next instr. is at Label
Formats:
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
funct
26 bit address
14
Machine Language

Instructions, like registers and words of data, are also 32 bits long
 Example: add $t0, $s1, $s2
 registers have numbers, $t0=9, $s1=17, $s2=18

Instruction Format:
000000 10001
op

rs
10010
rt
01000
rd
00000
100000
shamt
funct
Can you guess what the field names stand for?
15
MIPS Encoding: R-Type
31
26 25
opcode
21 20
rs
16 15
rt
11 10
rd
6
5
shamt
0
funct
rd
rt
add $4, $3, $2
rs
31
26 25
21 20
16 15
11 10
6
5
0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
opcode
rs
rt
rd
shamt
funct
0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
Encoding = 0x00622020
16
MIPS Encoding: R-Type
31
26 25
opcode
21 20
rs
16 15
11 10
rt
rd
6
5
shamt
0
funct
rd
shamt
sll $3, $5, 7
rt
31
26 25
21 20
16 15
11 10
6
5
0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0
opcode
rs
rt
rd
shamt
funct
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0
Encoding = 0x000519C0
17
Machine Language




Consider the load-word and store-word instructions,
 What would the regularity principle have us do?
 New principle: Good design demands a compromise
Introduce a new type of instruction format
 I-type for data transfer instructions
 other format was R-type for register
Example: lw $t0, 32($s2)
35
18
9
op
rs
rt
32
16 bit number
Where's the compromise?
18
MIPS Encoding: I-Type
31
26 25
opcode
21 20
rs
16 15
0
rt
Immediate Value
rt
Immediate
lw $5, 3000($2)
rs
31
26 25
21 20
16 15
0
1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
opcode
rs
rt
Immediate Value
1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
Encoding = 0x8C450BB8
19
MIPS Encoding: I-Type
31
26 25
opcode
21 20
rs
16 15
0
rt
Immediate Value
rt
Immediate
sw $5, 3000($2)
rs
31
26 25
21 20
16 15
0
1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
opcode
rs
rt
Immediate Value
1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
Encoding = 0xAC450BB8
20
Stored Program Concept


Instructions are bits
Programs are stored in memory
— to be read or written just like data
Processor

Memory
memory for data, programs,
compilers, editors, etc.
Fetch & Execute Cycle
 Instructions are fetched and put into a special register
 Bits in the register "control" the subsequent actions
 Fetch the “next” instruction and continue
21
Control

Decision making instructions
 alter the control flow,
 i.e., change the "next" instruction to be executed

MIPS conditional branch instructions:
bne $t0, $t1, Label
beq $t0, $t1, Label

Example:
if (i==j) h = i + j;
bne $s0, $s1, Label
add $s3, $s0, $s1
Label: ....
22
Control

MIPS unconditional branch instructions:
j label

Example:
if (i!=j)
h=i+j;
else
h=i-j;

beq $s4, $s5, Lab1
add $s3, $s4, $s5
j Lab2
Lab1: sub $s3, $s4, $s5
Lab2: ...
Can you build a simple for loop?
23
BEQ/BNE uses I-Type
31
26 25
opcode
21 20
rs
16 15
rt
0
Signed Offset Value
(encoded in words, e.g. 4-bytes)
rs
beq $0, $9, 40
rt
31
26 25
21 20
Offset
Encoded by
40/4 = 10
16 15
0
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
opcode
rs
rt
Immediate Value
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
Encoding = 0x1009000A
24
MIPS Encoding: J-Type
31
26 25
0
opcode
Target Address
•jal will jump and push
return address in $ra ($31)
•Use “jr $31” to return
Target
jal 0x00400030
X
0000 0000 0100 0000 0000 0000 0011 0000
Target Address
31
26 25
Instruction=4 bytes
0
0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
opcode
Target Address
0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
Encoding = 0x0C10000C
25
JALR and JR uses R-Type
 JALR (Jump And Link Register) and JR (Jump Register)
 Considered as R-type
 Unconditional jump
 JALR used for procedural call
jalr r2
Or
jalr r31, r2
jr r2
31
26 25
21 20
16 15
11 10
6
5
0
31
26 25
21 20
16 15
11 10
6
5
0
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 0 0 1
rd
opcode
rs
0
0
funct
(default=31)
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
0
opcode
rs
0
0
funct
26
Control Flow


We have: beq, bne, what about Branch-if-less-than?
New instruction:
if $s1 < $s2 then
$t0 = 1
slt $t0, $s1, $s2
else
$t0 = 0

Can use this instruction to build "blt $s1, $s2, Label"
— can now build general control structures
For ease of assembly programmers, the assembler allows “blt” as a
“pseudo-instruction”
— assembler substitutes them with valid MIPS instructions
— there are policy of use conventions for registers

blt $4 $5 loop

slt $1 $4 $5
bne $1 $0 loop
2 27
Constants



Small constants are used quite frequently (50% of operands)
e.g.,
A = A + 5;
B = B + 1;
C = C - 18;
Solutions? Why not?
 put 'typical constants' in memory and load them.
 create hard-wired registers (like $zero) for constants like one.
 Use immediate values
MIPS Instructions:
addi $29, $29, 4
slti $8, $18, 10
andi $29, $29, 6
ori $29, $29, 4
3 28
How about larger constants?


We'd like to be able to load a 32 bit constant into a register
Must use two instructions, new "load upper immediate" instruction
lui $t0, 1010101010101010
filled with zeros

1010101010101010
0000000000000000
Then must get the lower order bits right, i.e.,
ori $t0, $t0, 1010101010101010
1010101010101010
0000000000000000
0000000000000000
1010101010101010
1010101010101010
1010101010101010
ori
29
Input/Output
 Place proper arguments (e.g. system call code) to corresponding
registers and place a ‘syscall’
 Print string


li
la

syscall
$v0, 4
$a0, var
 Print integer



li $v0, 1
add $a0, $t0, $0
syscall
 Read integer


li $v0, 5
Syscall
# result in $v0
 See Appendix A for more.
30
Assembly Language vs. Machine
Language
 Assembly provides convenient symbolic
representation
 much easier than writing down numbers
 e.g., destination first
 Machine language is the underlying reality
 e.g., destination is no longer first
 Assembly can provide 'pseudoinstructions'
 e.g., “move $t0, $t1” exists only in Assembly
 would be implemented using “add $t0,$t1,$zero”
 When considering performance you should count real
instructions
31
Other Issues
 Things we are not going to cover
support for procedures
linkers, loaders, memory layout
stacks, frames, recursion
manipulating strings and pointers
interrupts and exceptions
system calls and conventions
 Some of these we'll talk about later
 We've focused on architectural issues
 basics of MIPS assembly language and machine code
 we’ll build a processor to execute these instructions.
32
Summary of MIPS
 simple instructions all 32 bits wide
 very structured
 only three instruction formats
R
op
rs
rt
rd
I
op
rs
rt
16 bit address
J
op
shamt
funct
26 bit address
 rely on compiler to achieve performance
— what are the compiler's goals?
 help compiler where we can
33
Addresses in Branches and Jumps

Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
j Label


Next instruction is at Label if $t4  $t5
Next instruction is at Label if $t4 = $t5
Next instruction is at Label
Formats:
I
op
J
op
rs
rt
16 bit address
26 bit address
Addresses are not 32 bits
— How do we handle this with load and store instructions?
34
Addresses in Branches


Instructions:
bne $t4,$t5,Label
beq $t4,$t5,Label
Formats:
I


Next instruction is at Label if $t4$t5
Next instruction is at Label if $t4=$t5
op
rs
rt
16 bit address
Could specify a register (like lw and sw) and add it to address
 use Instruction Address Register (PC = program counter)
 most branches are local (principle of locality)
Jump instructions just use high order bits of PC
 address boundaries of 256 MB
35
To Summarize
MIPS operands
Name
32 registers
Example
Comments
$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform
$a0-$a3, $v0-$v1, $gp,
arithmetic. MIPS register $zero always equals 0. Register $at is
$fp, $sp, $ra, $at
reserved for the assembler to handle large constants.
Memory[0],
2
30
Accessed only by data transfer instructions. MIPS uses byte addresses, so
memory Memory[4], ...,
words
and spilled registers, such as those saved on procedure calls.
add
MIPS assembly language
Example
Meaning
add $s1, $s2, $s3
$s1 = $s2 + $s3
Three operands; data in registers
subtract
sub $s1, $s2, $s3
$s1 = $s2 - $s3
Three operands; data in registers
$s1 = $s2 + 100
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
$s1 = Memory[$s2 + 100]
Memory[$s2 + 100] = $s1
Used to add constants
Category
Arithmetic
sequential words differ by 4. Memory holds data structures, such as arrays,
Memory[4294967292]
Instruction
addi $s1, $s2, 100
lw $s1, 100($s2)
sw $s1, 100($s2)
store word
lb $s1, 100($s2)
load byte
sb $s1, 100($s2)
store byte
load upper immediate lui $s1, 100
add immediate
load word
Data transfer
Conditional
branch
Unconditional jump
$s1 = 100 * 2
16
Comments
Word from memory to register
Word from register to memory
Byte from memory to register
Byte from register to memory
Loads constant in upper 16 bits
branch on equal
beq
$s1, $s2, 25
if ($s1 == $s2) go to
PC + 4 + 100
Equal test; PC-relative branch
branch on not equal
bne
$s1, $s2, 25
if ($s1 != $s2) go to
PC + 4 + 100
Not equal test; PC-relative
set on less than
slt
$s1, $s2, $s3
if ($s2 < $s3) $s1 = 1;
else $s1 = 0
Compare less than; for beq, bne
set less than
immediate
slti
jump
j
jr
jal
jump register
jump and link
$s1, $s2, 100 if ($s2 < 100) $s1 = 1;
Compare less than constant
else $s1 = 0
2500
$ra
2500
Jump to target address
go to 10000
For switch, procedure return
go to $ra
$ra = PC + 4; go to 10000 For procedure call
36
Addressing Mode
1. Immediate addressing
Operand is constant
op
rs
rt
Immediate
2. Register addressing
op
rs
rt
rd
...
funct
Registers
Operand is in register
Register
3. Base addressing
op
rs
lb $t0, 48($s0)
rt
Memory
Address
+
Register
Byte
Halfword
Word
4. PC-relative addressing
bne $4, $5, Label
op
(label will be assembled into
a distance)
rs
rt
Memory
Address
PC
+
Word
5. Pseudodirect addressing
j Label
op
Address
PC
Concatenation w/ PC[31..28]
Memory
Word
37
Supplementary Materials
38
Alternative Architectures
 Design alternative:
 provide more powerful operations
 goal is to reduce number of instructions executed
 danger is a slower cycle time and/or a higher CPI
 Sometimes referred to as “RISC vs. CISC”
 virtually all new instruction sets since 1982 have been RISC
 VAX: minimize code size, make assembly language easy
instructions from 1 to 54 bytes long!
 We’ll look at PowerPC and 80x86
39
PowerPC
 Indexed addressing
 example:
lw $t1,$a0+$s3
#$t1=Memory[$a0+$s3]
 What do we have to do in MIPS?
 Update addressing
 update a register as part of load (for marching through
arrays)
 example: lwu $t0,4($s3)
#$t0=Memory[$s3+4];$s3=$s3+4
 What do we have to do in MIPS?
 Others:
 load multiple/store multiple
 a special counter register “bc Loop”
decrement counter, if not 0 goto loop
40
80x86









1978: The Intel 8086 is announced (16 bit architecture)
1980: The 8087 floating point coprocessor is added
1982: The 80286 increases address space to 24 bits, +instructions
1985: The 80386 extends to 32 bits, new addressing modes
1989-1995: The 80486, Pentium, Pentium Pro add a few instructions
(mostly designed for higher performance)
1997: MMX (SIMD-INT) is added (PPMT and P-II)
1999: SSE (single prec. SIMD-FP and cacheability instructions) is added in P-III
2001: SSE2 (double prec. SIMD-FP) is added in P4
2004: Nocona introduced (compatible with AMD64 or once called x86-64)
“This history illustrates the impact of the “golden handcuffs” of compatibility
“adding new features as someone might add clothing to a packed bag”
“an architecture that is difficult to explain and impossible to love”
41
A Dominant Architecture: 80x86



See your textbook for a more detailed description
Complexity:
 Instructions from 1 to 17 bytes long
 one operand must act as both a source and destination
 one operand can come from memory
 complex addressing modes
e.g., “base or scaled index with 8 or 32 bit displacement”
Saving grace:
 the most frequently used instructions are not too difficult to build
 compilers avoid the portions of the architecture that are slow
“what the 80x86 lacks in style is made up in quantity,
making it beautiful from the right perspective”
42
Summary
 Instruction complexity is only one variable
 lower instruction count vs. higher CPI / lower clock rate
 Design Principles:




simplicity favors regularity
smaller is faster
good design demands compromise
make the common case fast
 Instruction set architecture
 a very important abstraction indeed!
43