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Compilation, Architectural Support, and Evaluation
of SIMD Graphics Pipeline Programs on a
General-Purpose CPU
Mauricio Breternitz Jr, Herbert Hum, Sanjeev Kumar
Microprocessor Research Labs,
Intel Corporation
Graphics Applications
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Computational intensive graphics applications
are becoming increasingly popular
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Computer-Aided Design
─
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From Airplanes to Cars
Visualization of massive quantities of Data
Visual Simulators e.g. Training Pilots
Fancier Graphical User Interfaces
And, of course, Games
And this trend is continuing
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As high-end applications become more mainstream
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3D Application
OpenGL Or DirectX
Graphics Pipeline
Scene
Transform
Lighting
Vertex Shaders
• Operate on every vertex in the scene
Clipping
• Effects like
• Blur
• Diffuse and specular reflection
Rasterization
Texture Mapping
Compositing
Display
Pixel Shaders
• Operate on every pixel
• Effects like
• Texturing
• Fog blending
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Vertex and Pixel Shaders
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Need to operate millions of times a second
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Small programs
Typically run on the graphics cards
However most desktops do not have graphics
cards that support programmable shaders
This work focuses on running Vertex Shaders
on the main CPU
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Pixel shaders have very high computational and
bandwidth requirements
Graphics applications are designed to adapt to the
available features and performance
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Goals
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Improving the performance of Vertex Shaders
on the main CPU
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Analyze the performance on today’s CPU
Better Compiler Optimizations
Additional Architectural Support
Identify three architectural and compiler
enhancements
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Significant impact on the performance
─
Roughly by a factor of 2
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Outline
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Motivation
Baseline Compiler
Three Enhancements
Performance Evaluation
Conclusions
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Vertex Shader Programs
Virtual
Machine
Temporary
Registers
12 x 4
Vertex Input
16 x 4 Registers
SIMD ALU
Integer
Registers
84 x 1
Constant
Memory
256 x 4
Vertex Output
15 x 4 Registers
dp4
dp4
dp4
dp4
oPos.x,
oPos.y,
oPos.z,
oPos.w,
v0,
v0,
v0,
v0,
c[0]
c[1]
c[2]
c[3]
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Small Programs (at most 256 instructions)
SIMD instructions with xyzw components
Mask and Swizzle on each instruction
No state saved between vertices
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mov
oD0, c[4].wzyx
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Read-only memory & Temporary Registers
Program cannot change control flow
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Baseline Optimizing Compiler
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Implemented a Compiler for Vertex Shaders
Input:
Vertex Shader Assembly
Output: Optimized x86 (with SSE2)
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Started with DirectX reference rasterizer: Interpreter
─
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Used it as the front end
Use Olive pattern-matching code-generator generator
Graph-coloring based register allocator
Loop unrolling
List-scheduler
About 70% faster than a naïve translator
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Translate into C and feed it to a C compiler
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Characteristics of Generated Code
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Mostly SIMD instructions (x86 with SSE2)
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Large basic blocks
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83-99 % instructions
Use of control-flow is limited
Makes it easier to compile efficiently
Vertex Shared Assembly to x86 Assembly
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10-20 times increase in number of instructions
mul
r0.x_z_, v0.xyzz,
Parallel Architecture and Compilation Techniques, 2003
v1.wwww
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Outline
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Motivation
Baseline Compiler
Three Enhancements
Performance Evaluation
Conclusions
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1. New Instructions
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Dot products are very common in Shaders
A dot product translates is expensive on x86
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A sequence of 7 instructions
1 multiply, 2 add, 4 shuffle instructions
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In the simple case
New dot product instructions
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Compute dot product of two source operands and
store it in each of the word of the destination
operand
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2. Mask Analysis Optimization
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Traditional optimizers keep track of the
liveness information on a per-register basis
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Analysis Phase
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Shaders: often only part of the SIMD register is live
Modify to do this for each word of the SIMD register
Annotate the IR with additional information
During live variable analysis, propagate the
liveness mask depending on the instructions
Optimization Phase
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Identify dead code
Replace some shuffle/mask instructions with move
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Might get eliminated entirely during register allocation
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3. Number of Registers
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Spilling registers to memory can degrade
performance
Investigate the impact of increasing the
number of registers from 8 to 16
Why not more?
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Trickier to encode it in the ISA
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Outline
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Motivation
Baseline Compiler
Three Enhancements
Performance Evaluation
Conclusions
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Experimental Setup
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10 Vertex Shaders
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2.2 GHz Pentium IV processor
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8-84 instructions
Only 3 of them have loops (Control)
Instruction counts otherwise
Breakdown the instructions into categories
Measure performance by using the generated
code to process an array of vertices
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Compute average
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Evaluation
Normalized
Execution Time
Base
New Instructions Only
Mask Optimization Only
Both
1
0.8
0.6
0.4
0.2
0
B
CTC
L
PS
PL
PE
R
T
TS
W
Vertex Shaders
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New dot-product Instructions: 27.4% Average (Estimate)
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Reduces the number of instructions by 24 %
Mask optimization: 19.5% on Average
Both: 42% on Average
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Evaluation Cont’d
Normalized
Instruction Count
Base
16 Registers
1
0.8
0.6
0.4
0.2
0
B
CTC
L
PS
PL
PE
R
T
TS
W
Vertex Shaders
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Reduce the number of instructions by 8 % on average
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35-100% of the spill instructions
This understates the potential benefit
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More registers allow more aggressive optimizations like
instruction scheduling
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Outline
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Motivation
Baseline Compiler
Three Enhancement
Performance Evaluation
Conclusions
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Conclusions & Future Work
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Implemented an Optimizing Compiler for
Vertex Shaders
Propose and Evaluate Three Enhancements
Compiler: Mask Optimization
 Architectural: New Instructions & More registers
Improve the performance by a factor of 2 (Roughly)
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Shaders are evolving rapidly
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More like general purpose processors
More complex model
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