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240-208
Fundamental of Computer Architecture
November 01, 2003
By Panyayot Chaikan
[email protected]
Chapter 2
รูปแบบของข้ อมูลในคอมพิวเตอร์
Data representation in computer
240-208 Fundamental of Computer Architecture
Chapter 2 - Data Representation in Computer
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เนื้อหา
รู ปแบบการจัดเก็บข้อมูลลงบนคอมพิวเตอร์
ตัวเลขฐานสองแบบมีเครื่ องหมาย
Overflow ของการกระทาทางคณิ ตศาสตร์ของตัวเลข
เลขทศนิยมแบบ Fixed-Point
เลขทศนิยมแบบ Floating-Point
การกระทาทางคณิ ตศาสตร์กบั เลขทศนิยมแบบ Floating-Point
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Number representation
ลองพิจารณาตัวเลข
B = bn-1.....b1b0
เมื่อ

bi = 0 หรื อ 1
j 0  i  n  1
ค่ าของ B หาได้ จาก
Value of B = bn-1 x 2n-1 + .... + b1x 21
+ b0 x 20
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Binary, signed-integer representations
ตัวเลขฐานสอง B
ค่ าของ B ในระบบเลขต่ างๆ
b3b2b1b0
Sign and magnitude 1’s complement
2’s complement
0111
0110
0101
0100
0011
0010
0001
0000
1000
1001
1010
1011
1100
1101
1110
1111
+7
+6
+5
+4
+3
+2
+1
+0
-0
-1
-2
-3
-4
-5
-6
-7
240-208 Fundamental of Computer Architecture
+7
+6
+5
+4
+3
+2
+1
+0
-7
-6
-5
-4
-3
-2
-1
-0
+7
+6
+5
+4
+3
+2
+1
+0
-8
-7
-6
-5
-4
-3
-2
-1
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Addition/Subtraction of Signed numbers
2’s complement is the most efficient method
0010
(+2)
1011
(-5)
0011
(+3)
1110
(-2)
0101
(+5)
1001
(-7)
1101
(-3)
1101
(-3)
1001
(-7)
0111
(+7)
????
(+4)
0100
(+4)
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Addition/Subtraction of Signed numbers
Use only Adder
Subtraction:Perform 2’s complement with
subtrahend
1101
(-3)
1101
(-3)
0100
(+4)
1100
(-4)
????
(-10)
1001
(-7)
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Chapter 2 - Data Representation in Computer
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Addition/Subtraction of Signed numbers
A
adder
B
2'complement
'1' when +
'0' when -
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Chapter 2 - Data Representation in Computer
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Overflow in Integer arithmetic
4-bit signed number ranges from -8...+7
the result from addition
more than +7
or less than -8, overflow occurred
1101
(-3)
1101
(-3)
0111
(+7)
1001
(-7)
????
(-10)
0110
(+6)
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Overflow
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Overflow
Overfolow detection rules:
1. Overflow can occur only when adding 2 numbers
that have the same sign
2. When adding X and Y, overflow occurs when the
sign of result is not the same as the sign of X and Y
Xs
+
Ys
Ov
=(XS YS RS) + (XS YS RS)
Rs
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Number representation
We always represent a number in the 2’s
complement system
4 bit
-8...+7
8 bit
-128...+127
16 bit
-32768....+32767
32 bit
-2147483648....
+2147483647
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Sign extension
To represent 2’s complement signed number
using larger number of bits, repeat the sign bits as
many times as needed to the left
for example : convert 4 bits to 8 bits
1001
(-7)
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11111001(-7)
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Characters

ASCII : American Standard Code for Information Interchange
ที่มาของรู ป http://www.jimprice.com/ascii-0-127.gif
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Memory location and Addresses
Memory consists of many millions of storage cells,each
of which can store a bit of information (0/1)
memory is organized into a group of n bits can be
stored or retrieved in a single, basic operation
Each group of n bits is referred to as a word of
information
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Memory location and Addresses
Bit, byte, word
A unit of 8
bit is called byte
Word length typically ranges from 16 to 64 bits
CPU access data in memory for 1 word at a time
n bits
1st word
2nd word
3rd word
:
:
last word
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Word
32-bit word can store
32-bit 2’s complement number
four ASCII characters
32 bits
b31
b1
b0
8 bits
8 bits
8 bits
8 bits
ascii
character
ascii
character
ascii
character
ascii
character
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Memory accessing
To access the memory, addresses for each
memory location is required
Addresses range from 0 through 2k-1 for 2k
address space
24-bit address generates address space of 224
or 16,777,216 locations.
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Byte addressable memory
most modern computer
have successive addresses
refer to successive byte location in the memory
Byte locations have address 0,1,2,3.....
Successive words are located at addresses
0,4,8,12,.... (for 32-bit machine)
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Big-Endian and Little-Endian assignments
2
ways to assign byte address across words
big endian
little endian
0
0
1
2
3
0
3
2
1
0
4
4
5
6
7
4
7
6
5
4
k
k
:
:
:
k
k
k
:
:
:
k
k
2-4
2-4
2-3
2-2
2-1
word address
byte address
240-208 Fundamental of Computer Architecture
k
k
k
2-4
2-1
2-2
2-3
2-4
word address
byte address
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Little endian VS Big endian
big-endian
little-endian
0
20H
0
9AH
1
1FH
1
53H
2
53H
2
1FH
3
9AH
3
20H
4
4
5
5
6
6
ข ้อมูลทีเ่ ก็บ : 201F539AH
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Little endian VS Big endian
ข ้อมูลทีเ่ ก็บ : 201F539AH
6
6
5
5
4
4
3
9AH
3
20H
2
53H
2
1FH
1
1FH
1
53H
0
20H
0
9AH
big-endian
240-208 Fundamental of Computer Architecture
little-endian
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Word alignment
For Example: keeping value 201F539AH in
memory
0
4
20
0
20
1F
53
9A
4
k
53
9A
:
:
:
2-4
word address
1F
:
:
:
k
byte address
aligned address
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2-4
word address
byte address
unaligned address
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Fixed-point number
B = b0.b-1b-2.....b-(n-1)
Sign bit
F(B) = (- b0 x 20)+ (b-1 x 2-1)+(b-2 x 2-2)+... + (b-(n-1))
x
2
(n-1)
-1
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F 
(1-2-(n-1))
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Fixed-point number
F(B) =
1.1001011
F(B)
= (- 1 x 20)+ (1 x 2-1)+(0 x 2-2)+(0 x 2-3)+(1 x 2-4)+(0
x 2-5)+(1 x 2-6)+(1 x 2-7)
=1+0.5+0+0+0.0625+0+0.015625+0.0078125
= -0.4140625
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Fixed-point number
32-bit, signed, fixed point represent value range
approximately 4.55*10-10 to 1
This is not sufficient for scientific caclulation such as
Avogadro’s number
Planck’s constant
240-208 Fundamental of Computer Architecture
6.0247*1023 mole-1
6.6254*10-27 erg. s
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Floating-point number
General form for floating point number in
decimal system
+X1.X2X3X4X5X6X7*10+Y1Y2
exponent
Significant digits
When the decimal point is placed to the right of
the first(nonzero) significant digit, the number is
said to be normalized
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IEEE standard floating-point format
32 bits
S
Sign bit
E'
8-bit signed exponent in excess-127
representation
M
23-bit mantissa fraction
Value represented = + 1.M x 2 E’-127
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IEEE standard floating-point format
32 bits
S
E'
M
Value represented = + 1.M x 2 E
E =signed exponent
E’ = E + 127
1 < E’ < 254, 0 and 255 are used to represent special
values
-126 < E < 127
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Special Values
32 bits
S
E'
M
E’ = 0 and M = 0 -----> 0
E’ = 255 and M = 0 -----> 
E’ = 0 and M ≠ 0 -----> denormal number
E’ = 255 and M ≠ 0 -----> NaN (not a number)
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floating-point format : Example
0 00101000 . 0010110.......
1
1.0010110….1 x 2-87
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Normalized vs unnormalized value
0 10001000 . 0010110.......
0.0010110…. x 29
Unnormalized value
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Normalized vs unnormalized value
0 10000101 . 0110.......
1. 0110…. x 26
Normalized value
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Floating-point Add/Subtract rule
1. Choose the number with the smaller exponent
and shift its mantissa right a number of steps
equal to the difference in exponents
2. Set the exponent of the result equal to the larger
exponent
3. Perform addition/subtraction on the mantissas
4. Normalize the resulting value, if necessary
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Floating-point Add/Subtract:Example
2.9400 x 102 + 4.3100 x 104
= 0.0294 x 104 + 4.3100 x 104
= 4.3688 x 104
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Floating-point Multiply rule
1. Add the exponents and subtract 127
2. Multiply the mantissas and determine the sign
of the result
3. Normalize the resulting value, if necessary
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Floating-point Multiply:Example
2.9400 x 102 x 4.3100 x 104
= (2.9400 x 4.3100) x 10 (2+4)
= 12.6714 x 106
= 1.26714 x 107
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Floating-point Divide rule
1. Subtract the exponents and add 127
2. Divide the mantissas and determine the sign of
the result
3. Normalize the resulting value, if necessary
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Floating-point Divide:Example
4.3100 x 104 ÷ 2.9400 x 102
= (4.3100 ÷ 2.9400) x 10 (4-2)
= 1.46598… x 102
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จบ บทที่ 2
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Chapter 2 - Data Representation in Computer
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