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COSC 3213: Computer Networks I
Instructor: Dr. Amir Asif
Department of Computer Science
York University
Section M
Topics:
1. Error Detection Techniques: Single Parity and 2D Block Parity
2. Polynomial Code
3. CRC Code
Garcia: Sections 3.5 – 3.8
Error Detection and Correction
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Even with optimal transmission system, bit errors occur because of the noisy channel.
Bit errors occur in random and are therefore defined in terms of their probability of
occurrence.
Probability of bit error = (No. of bits in error)/(Total no. of bits transmitted).
Common values for Probability of bit error:
Wireless ~ 10-3
Copper wires ~ 10-6
Optical fibre ~ 10-9
There are two approaches to error control
Automatic Repeat Request (ARQ): On the detection of error, the transmitter is asked to
retransmit.
Forward Error Correction (FEC): On the detection of error, the receiver tries to correct the
error itself. FEC is appropriate when a return channel is not available or retransmission
requests can not be accomodated.
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Single Parity Bit Detection
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Parse data in blocks of k-bits.
Add a single parity bit to make the numbers of 1’s even (or odd) to a block of data. If the total
number of 1’s are made even, the scheme is called “even parity” scheme. (If the total number
of 1’s are made odd, the scheme is called “odd parity” scheme.)
The block of data is transmitted along with the parity bit.
The receiver counts the number of 1’s in the received block. If the number of 1’s are even for
an even parity bit scheme, transmission is assumed error- free.
The parity bit is discarded and the remaining data is passed on to the application.
Redundancy ratio of 2D parity check scheme = 1/k.
Activity 1: Suppose a transmitter is transmitting 1110001. What is the transmitted data if even
parity is used? Repeat for odd parity.
Activity 2: Given that even number of errors will not be detected with a single bit parity scheme,
calculate the probability of an error going undetected in problem 1 if the probability of error in
a single bit is 10-3.
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2D Parity Checks
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Arrange k-information bits in a 2D (m × n) array.
Create the parity bit for each column and row based on the even parity bit scheme.
Transmit the new (m + 1) × (n + 1) array.
All single, double, and triple bit error patterns are detected. Some four bit error patterns may
not be detected.
Redundancy ratio of 2D parity check scheme = (m + n + 1)/k.
2D Parity Check code is used by the early data link layers.
Activity 3: Using an (5 × 4) array, generate the 2D parity check code for the information bits
10010
01000
10010
11011.
Activity 4: The (5 × 4) array generated in Activity 2 is transmitted. If the received data bits are
100100 000001 100100 110110 100111, determine if an error has occurred.
Repeat for the received data bits 100100 000001 100100 100110 100111.
Repeat for the received data bits 100100 000101 100100 100110 100111.
Repeat for the received data bits 100100 000101 100100 100010 100111
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Check Sum
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Several Internet protocols (IP, TCP, and UDP) use check bits to detect errors in the header of
the PDU.
Scheme is based on the following steps:
Assume the header consists of L words with each word 16-bit long.
b0 b1 b2 ∙∙∙ bL-1 plus a checksum word bL
Add 16-bit word using modulo-16 arithmetic
x = b0 b1 b2 ∙∙∙ bL-1 plus a checksum word bL
The checksum is generated by taking the additive inverse of x in modulo-16 arithmetic.
Activity 3: Assuming 4-bit words and L = 3, generate the checksum for 1100 1010.
Activity 4: Implement the check sum algorithm using modulo-2 arithmetic.
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Cyclic Redundancy Code
Example: Generate the (15,10) CRC sequence for message M = 1010001101 using the generator
pattern P = 110101?
Step # 1: Evaluate the values of k and n.
k = 10, n = 5
Step # 2: Determine the information polynomial of degree (k – 1).
i(x) = x9+x7+x3+x2+1
Step # 3: Determine the generator polynomial of degree (n – k).
g(x) = x6+x5+x3+x
Step # 4: Multiply the information polynomial with xn-k.
x5i(x) = x14+x12+x8+x7+x5
Step # 5: Calculate the remainder obtained by dividing x5i(x) with g(x) . rem(x5i(x),g(x)) = x3+x2+x
Step # 6: Add the remainder obtained in step # 5 to x5i(x) to generate the CRC codeword.
CRC codeword = x14+x12+x8+x7+x5+ x3+x2+x
or,
101000110101110
Step # 7: The CRC codeword is transmitted to the receiver.
Receiver:
Step # 1: Generator generator polynomial is known.
Step # 2: Divide the received polynomial with the generator polynomial . If the remainder is 0,
error- free transmission is assumed. If the remainder is not 0, error has occurred.
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