Download Document

ECE 424 Design of Microprocessor-Based Systems
Fundamentals of Digital Logic
and Binary Number Representation
Haibo Wang
ECE Department
Southern Illinois University
Carbondale, IL 62901
2-1
Digital Signals and Basic Logic Gates
 Digital signal values
True
1
High Voltage (e.g. 5V)12
False
0
Low Voltage (e.g. 0V)
 Basic logic gates
1. Inverter
2. AND
3. NAND
X
X
Y
X
Y
X
Y
1
0
0
1
X
Y
Z
0
0
1
1
0
1
0
1
0
0
0
1
Y=X
Z=XY
Z=XY
Truth Table of
an inverter
Truth Table of
an AND gate
2-2
Basic Logic Gates
4. OR
5. NOR
4. XOR
X
Y
X
Y
X
Y
Z=X+Y
X
Y
Y
Z
0
0
1
1
0
1
0
1
0
1
1
1
X
Y
Z
0
0
1
1
0
1
0
1
0
1
1
0
Truth Table of
an OR gate
Z=X+Y
Z = XY +XY
Z=X+Y
5. XNOR
X
Truth Table of
an XOR gate
Z = XY +XY
Z=X+Y
2-3
Basic Logic Gates
 Tri-state Buffer
I
O
C
C
I
O
1
0
0
X
0
1
Z
0
1
Truth table of a
tri-state buffer
I1
O
X
Y
I2
S
Mux
2-to-1 multiplexer
C
Bi-direction circuit
2-4
Decoder Circuits
 A decoder circuit uniquely selects one of its outputs according to its
input signals
Decoder


N inputs
2N outputs
 2-to-4 decoder implementation
X
X Y
0
0
1
1
0
1
0
1
Z1 Z2 Z3 Z4
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
Z1 (00)
Z2 (01)
Y
Z3 (10)
Z4 (11)
2-5
Decoder Circuit
 3-to-8 decoder implementation
 Assume that we have 2-to-4 decoders available as standard components
 When CS is low (0), all the outputs of the decoder are
low (0)
X
X
Y
Y
X
Y
CS
2-to-4 decoder
CS
Z
X
Y
CS
2-6
Sequential Logic Circuits
 D latch
D
Q
CLK
Q
D
CLK
Q
 When CLK=1, Q always reflects the signal value at input D
 If CLK=0, Q stores the last D value which appears at D just before CLK falls to 0
 D Flip-flop
D
Q
CLK
Q
D
CLK
Q
 D flip-flop will not change its output values unless there is a negative edge event
at CLK input (CLK switches from logic 1 to 0).
 When a negative edge appears at CLK input , D Flip-flop updates Q to the current D value
2-7
Sequential Logic Circuits
 Counter
 Basic binary counter
A
CLK
DFF
Q
D
Q
B
C
DFF
Q
D
Q
DFF
Q
D
Q
 Synchronous counter
B
A
DFF
Q
D
Q
DFF
Q
D
Q
C
D
Clk
C
B
A
Init.
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
Q
Q
CLK
2-8
Sequential Logic Circuits
 frequency divider
 Divide clock frequency by 4
CLK
DFF
Q
D
Q
DFF
Q
D
Q
CLK
CLK_4
CLK_4
 Divide clock frequency by 3
DFF
Q
D
Q
DFF
Q
D
Q
CLK
CLK_3
CLK_3
CLK
2-9
Sequential Logic Circuits
 Register
 A row of storage elements (e.g. D flip-flops)
Q3
DFF
Q
D
Q
Q2
DFF
Q
D
Q
Q1
DFF
Q
D
Q
Q0
Q[3:0]
DFF
Q
D
Q
Data
CLK
 Shift register
Q3
0
CLK
DFF
Q
D
Q
Q2
DFF
Q
D
Q
Q1
DFF
Q
D
Q
Q0
DFF
Q
D
Q
CLK
Q3
Q2
Q1
Q0
Init.
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
0
2-10
Memories Circuits
 Memories are storage devices containing a large number of
storage locations


N/2 bit
address
Row decoder
 Addressing space: total number of memory locations
 If a memory device has N bit addresses, it has 2N memory locations
Memory
location

Column decoder

N/2 bit address
2-11
Memory Types
 ROM v.s. RAM
 ROM: Read-Only Memory
 RAM: Random Access Memory (allow both read and write operations)
 Volatile v.s. Non-volatile
 Volatile:
memory loses data after power is off
 Non-volatile: memory keep stored data even after power is off
Non-volatile
Mask
ROM
PROM
EPROM
EEPROM
Volatile
Flash
memory
MRAM
SRAM DRAM
2-12
Memory Addressing
 Example
 Use memory chips with the capacity of 1K (1024 bit) to construct a 2K
memory system
1K
1K
W/R CS
W/R CS
Addr[9:0]
Addr[10]
W/R
2-13
Binary Number System
 Converting binary numbers to decimal numbers
Binary
Decimal
1011
 1*2^3 + 0*2^2 + 1*2^1 + 1*2^0
= 11
0111
 0*2^3 + 1*2^2 + 1*2^1 + 1*2^0
= 7
 Converting binary numbers to hexadecimal numbers
1 1 1 1 0 1 0 1 1 0 1 0 0 0 1 1
F
5
A
3
2-14
Binary Addition
 Example
 A single-bit full adder
A
0 1 0 1
+
1 0 0 1
1 1 1 0
C_in
B
Full
adder
C_out
S
 4-bit adder
A[0] B[0]
C_in
Full
adder
S[0]
A[1] B[1]
C_0
Full
adder
S[1]
A[2] B[2]
C_1
Full
adder
S[2]
A[3] B[3]
C_2
Full
adder
C_out
S[3]
2-15
Handling Negative numbers
 Signed magnitude
 The left-most bit is a sign bit
0 indicates positive a number and
1 indicates negative a number
 One’s complement
 For positive number A, it is
represented as usual binary number
 For negative number -A, its
representation is obtained by flipping
the bits of the binary representation of A
Signed magnitude Decimal
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1’s complement
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
0
1
2
3
0
-1
-2
-3
Decimal
0
1
2
3
0
-1
-2
-3
2-16
Handling Negative numbers
2’s complement
 Two’s complement
 For positive number A, it is the
same as the one’s complement
 For negative number A, add one
to the one’s complement
representation
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1
0
1
0
Decimal
0
1
2
3
-1
-2
-3
-4
 By using two’s complement number representation, minus operations
can be performed by adders
3
 1
2
0 1 1
1 1 1
2
 3
1 0 1 0
-1
+
Overflow
Ignore
2
+
0 1 0
1 0 1
1 1 1
-1
2-17