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Transcript
Analog IC Design
- Filters Yves Leduc,
Advanced System Technology,
Wireless Terminals Business Unit
Texas Instruments Inc.
YLD 10/2/99
ESINSA
-1-
Introduction
YLD 10/2/99
ESINSA
-2-
Analog? Digital?
A communication channel can support a digital or an
analog signal.
By the way,
what is an Analog Signal?
what is a Digital Signal?
YLD 10/2/99
ESINSA
-3-
A Hint.
There is obviously a difference:
YLD 10/2/99
ESINSA
-4-
Analog and Digital Signals
Too
easy
The representation
of a digital signal is
a sequence of
integer numbers.
But analog and
digital signals are
sharing the same
physical units.
Their values are
represented by
real numbers.
YLD 10/2/99
ESINSA
-5-
Confused?
The confusion exists.
The IC design addresses two fields:
• Physics:
the electrical realization.
• Mathematics:
the representation of a signal.
We are interested by the electrical realization affecting
the representation of the signal.
YLD 10/2/99
ESINSA
-6-
Analog Signal
“The physical values of an analog signal belong to a unique and
continuous domain of values.”
1.00
It does not mean that
an analog signal is
continuous.
It does not mean that
an analog circuit must be
linear.
0.00
YLD 10/2/99
Signal and noise coexist.
ESINSA
-7-
Digital Signal
“The physical values of a digital signal (when settled) belong to at
least two distinctive domains. In each domain, the representation of
the signal is unique.”
1
0
YLD 10/2/99
It does not mean that
a digital signal has
only 2 representations
(‘ 0 and 1 ’).
The gaps between
domains build noise
margins.
ESINSA
-8-
An Analog Signal
• can be translated.
offset + in[t]
• can be amplified.
gain * in[t]
• can be filtered.
H[s] * in[s]
• can be shaped.
Min[ in[t] , 3.0 ]
• can be sampled.
in[ti]
ti <= t < ti+1
• can be quantized.
qn
qn <= in[t] < qn+1
• can be converted
n
qn <= in[t] < qn+1
• can be damaged…
 in[t]
YLD 10/2/99
ESINSA
-9-
A Digital Signal
To process correctly a digital signal, a digital circuit
must be regenerative, i.e. non linear and active.
A digital signal, noisy, distorted or attenuated, must be
reshaped.
• Non linearity provides the necessary discrimination and
allows the reshaping of the signal.
• Amplification is needed to recover from the natural
attenuation.
YLD 10/2/99
ESINSA
- 10 -
Digital Signal Processing
The Digital Signal Processing is based on
the mathematical representation of the
signal, on an abstraction.
A sequence of numbers can be translated,
amplified, filtered, shaped, sampled,
quantized, converted, and … damaged as
an analog signal.
The sampled analog signal processing and
the digital signal processing are based on
the same mathematics.
YLD 10/2/99
0.010
0.005
0.015
0.495
0.725
0.780
0.805
0.830
0.855
0.900
...
ESINSA
- 11 -
Analog Signal Processing
1.00
In a Continuous Time
Domain.
0.00
1.00
In a Sampled Domain.
YLD 10/2/99
0.00
ESINSA
- 12 -
“Mixed Signal Design”
1.00
0.010
0.005
0.015
0.495
0.725
0.780
0.805
0.830
0.855
0.900
...
0.00
1.00
0.00
YLD 10/2/99
Converters,
Filters, ..
ESINSA
- 13 -
Filtering.
At some point in the process of
a signal, it is necessary to
suppress spurious components.
The characteristics of a filter
are very depending on the
frequency.
Filters are implemented in the
continuous time or the sampled
analog domain, or in the digital
domain.
YLD 10/2/99
Continuous Time
Analog Domain
Sampled
Analog Domain
f
Digital
Domain
f
ESINSA
- 14 -
Be consistent. And careful (1).
What physical characteristics are coding the representation of
the signal?
Voltage, Current, Frequency, Phase, Transition, ..?
Continuous time domain, Sampled domain?
Filtering should not damage the representation of the signal.
YLD 10/2/99
ESINSA
- 15 -
Be consistent. And careful (2).
1.00
Is it a sampled signal?
Is it a (poor) reconstruction
of the sampled signal in the
continuous time domain?
Passing back and forth from
the sampled to the
continuous time domain
requires specific techniques!
YLD 10/2/99
0.00
ESINSA
- 16 -
Basic Elements.
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ESINSA
- 17 -
Cost.
Cost. Cost.
Cost. Cost. Cost.
Performances are granted.
There is a price for the Differentiation.
The Cost of Ownership is a major driving factor:
• BOM (Bill Of Materials)
• Cost Overhead
YLD 10/2/99
ESINSA
- 18 -
Just Cost.
Integration is often (*) a solution to meet the cost:
• it may provide a differentiation
• it may reduce the BOM
• it may reduce the cost of the implementation
• it increase your market shares
• ...
(*) ‘often’ does not mean ‘always’
YLD 10/2/99
ESINSA
- 19 -
IC elements.
Transistors:
Capacitors:
Resistors:
MOSFET
 ..   
Bipolar, JFET

Vertical, Lateral

MOSFET

Polysilicon, Bulk Silicon, Metal,
 ..  
MOSFET
Inductors:
Metal, Bonding Wire
  ..   
Wires:
Several levels of Metal

Pads:
Metal

YLD 10/2/99
ESINSA
- 20 -
MOS Transistors.
Performances:
Factor Of Merit:
Major Parameters
Speed
(digital, analog)
Gain, Noise
(analog)
Gm / Cox
(digital, analog)
Gm / Gds
(analog)
Matching
(analog)
Effective Length
G
Photolithography
Process Features
Layout Care
YLD 10/2/99
S
D
B
ESINSA
- 21 -
MOS Transistors.
Factor of Merit:
NMOS / PMOS  3
Minimum Channel Size:
 1 m2
(Idem, low noise input)
 100 .. 1000
Gate Oxide:
 5 .. 10 nm
Best Practical Matching:
  0.1%
Absolute Value Spread:
(*)
m2
S
D
B
G
G
S
D
(*) sensitive information
YLD 10/2/99
B
ESINSA
- 22 -
Capacitors.
Performances:
Factor of Merit:
Major Parameters
YLD 10/2/99
Linearity
P2
Matching
Memory Effect
Ceff / Cpar
P1
Density (F / m2)
B
Absolute Value Spread
Dielectric and Dielectric Interface
Symmetry
Layout Care
ESINSA
- 23 -
Vertical Capacitors
Electrodes:
Polysilicon, Metal
Dielectric:
SiO2, Si3N4, ..
Factor of Merit:
Ceff / Cpar  10
Density:
 1 fF / m2
Best Practical Matching:
  0.1%
Absolute Value Spread:
  5%
Electrode 2
Electrode 1
Bulk
YLD 10/2/99
ESINSA
- 24 -
Lateral Capacitors
Factor of Merit:
Ceff / Cpar  (*) ..
Density:
 (*) / m2
Best Practical Matching:
  (*) %
Absolute Value Spread:
  (*) %
Electrode 1
Electrode 2
Bulk
Conventional shape or fractal.
(*) no reliable data yet available in the public domain.
YLD 10/2/99
ESINSA
- 25 -
Resistors.
Performances:
Factor of Merit:
Major Parameters
Voltage Coefficient
Temperature Coefficient
Matching
Density ( / m2)
Resistance / Parasitic Capacitance
Absolute Value Spread
Photolithography
Layout Care

B
YLD 10/2/99
ESINSA
- 26 -
Polysilicon Resistors
Resistivity:
20 .. 500  / 
Best Practical Matching:
  0.1 %
Absolute Value Spread:
 5%
Temperature Coefficient:
process dependent
Voltage Coefficient:
good
Bulk
YLD 10/2/99
ESINSA
- 27 -
Bulk Resistors
Resistivity:
1 .. 5000  / 
Best Practical Matching:
  0.1 %
Absolute Value Spread:
 5%
Voltage Coefficient:
fair or poor, process dependent.
Temperature Coefficient:
process dependent
Bulk
Doped Area
YLD 10/2/99
ESINSA
- 28 -
A Few Sizes

10 m2
LNA MOS Transistor

500
m2
Precision Resistor 1 k

500 m2
Capacitor 1 pF

1 000 m2
Bonding Pad

10 000 m2
Inductor 5 nH

250 000 m2
Small IC
 10 000 000 m2
Big IC
 100 000 000 m2
MOS Transistor
YLD 10/2/99
RC FILTERS
[including connections]
ESINSA
- 29 -
Conclusions
Inductors are left for RF designs.
External components should be avoided!
Integrated R*C is the preferred time constant to build the poles
and zeroes of IC filters.
MOS transistors are appealing but are intrinsically non linear.
YLD 10/2/99
ESINSA
- 30 -
R*C (1)
The absolute resistance of an integrated resistor depends on:
• Material resistivity (doping, granularity, ..)
• Material thickness.
• (Photolithography)
The absolute capacitance of an integrated capacitor depends on:
• Thickness of the dielectric material.
• Dielectric constant
• (Photolithography)
YLD 10/2/99
ESINSA
- 31 -
R*C (2)
The time constant depends on 2 uncorrelated values: R and C
R with a sigma of 5%
C with a sigma of 5%
It is impossible to rely on R*C to build accurate filters
at a correct cost.
So what?
YLD 10/2/99
ESINSA
- 32 -
Exercise 1
Optimize
YLD 10/2/99
=R*C
ESINSA
- 33 -