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EECS 105 Fall 2004, Lecture 42 Lecture 42: Review of active MOSFET circuits Prof. J. S. Smith Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Final Exam Covers the course from the beginning Date/Time: SATURDAY, MAY 15, 2004 8-11A Location: BECHTEL auditorium One page (Two sides) of notes Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Observed Behavior: ID-VDS VGS 4V I DS / k non-linear resistor region resistor region I DS “constant” current VDS VGS 3V VGS VGS 2V VDS For low values of drain voltage, the device is like a resistor As the voltage is increases, the resistance behaves non-linearly and the rate of increase of current slows Eventually the current stops growing and remains essentially constant (current source) Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Observed Behavior: ID-VDS VGS 4V I DS / k non-linear resistor region resistor region I DS “constant” current VDS VGS 3V VGS VGS 2V VDS As the drain voltage increases, the E field across the oxide at the drain end is reduced, and so the charge is less, and the current no longer increases proportionally. As the gate-source voltage is increased, this happens at higher and higher drain voltages. The start of the saturation region is shaped like a parabola Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Finding ID = f (VGS, VDS) Approximate inversion charge QN(y): drain is higher than the source less charge at drain end of channel Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Inversion Charge at Source/Drain The charge under the gate along the gate, but we are going to make a simple approximation, that the average charge is the average of the charge near the source and drain QN ( y 0) QN ( y L) QN ( y ) 2 QN ( y 0) Cox (VGS VTn ) QN ( y L ) Cox (VGD VTn ) VGD VGS VDS Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Average Inversion Charge Source End Drain End Cox (VGS VT ) Cox (VGD VT ) QN ( y ) 2 Cox (VGS VT ) Cox (VGS VSD VT ) QN ( y ) 2 Cox (2VGS 2VT ) CoxVSD VDS QN ( y ) Cox (VGS VT ) 2 2 Charge at drain end is lower since field is lower Notice that this only works if the gate is inverted along its entire length If there is an inversion along the entire gate, it works well because Q is proportional to V everywhere the gate is inverted Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Drift Velocity and Drain Current “Long-channel” assumption: use mobility to find v v( y ) n E ( y ) n (V / y ) nVDS L And now the current is just charge per area, times velocity, times the width: VDS VDS I D WvQN W Cox (VGS VT ) L 2 V W I D Cox (VGS VT DS )VDS L 2 Inverted Parabolas Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Square-Law Characteristics TRIODE REGION Boundary: what is ID,SAT? SATURATION REGION Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith The Saturation Region When VDS > VGS – VTn, there isn’t any inversion charge at the drain … according to our simplistic model Why do curves flatten out? Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Square-Law Current in Saturation Current stays at maximum (where VDS = VGS – VTn ) VDS W I D Cox (VGS VT )VDS L 2 I DS , sat V V W Cox (VGS VT GS T )(VGS VT ) L 2 W Cox I DS , sat (VGS VT ) 2 L 2 Measurement: ID increases slightly with increasing VDS model with linear “fudge factor” I DS , sat Department of EECS W Cox (VGS VT ) 2 (1 VDS ) L 2 University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith A Simple Circuit: An MOS Amplifier Input signal Supply “Rail” RD VDD vo vs vGS VGS vs Department of EECS VGS I DS Output signal University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small Signal Analysis Step 1: Find DC operating point. Calculate (estimate) the DC voltages and currents (ignore small signals sources) Substitute the small-signal model of the MOSFET/BJT/Diode and the small-signal models of the other circuit elements. Solve for desired parameters (gain, input impedance, …) Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith A Simple Circuit: An MOS Amplifier Input signal RD VDD Supply “Rail” vo vs vGS VGS vs Department of EECS VGS I DS Output signal University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Analysis Step 1. Find DC Bias – ignore small-signal source IGS,Q VGS,BIAS was found in Lecture 15 Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Modeling What are the small-signal models of the DC supplies? Shorts! Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Models of Ideal Supplies Small-signal model: isupply gsupply vsupply rsupply 0 short gsupply isupply vsupply 0 rsupply open Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Circuit for Amplifier Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Low-Frequency Voltage Gain Consider first 0 case … capacitors are open-circuits vout gmvs RD || ro Av gm RD || ro Design Variable Transconductance 2 I D,SAT W gm nCox (VGS VT ) L VGS VT Design Variables Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Voltage Gain (Cont.) Substitute transconductance: 2 I D,SAT Av RD || ro VGS VT g m RD Output resistance: typical value n= 0.05 V-1 1 ro I n D , SAT Voltage gain: Department of EECS 1 k 200 k 0.05 0.1 2 0.1 Av 25 || 200 14.3 0.32 University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Input and Output Waveforms Output small-signal voltage amplitude: 14 x 25 mV = 350 Input small-signal voltage amplitude: 25 mV Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith What Limits the Output Amplitude? 1. vOUT(t) reaches VSUP or 0 … or 2. MOSFET leaves constant-current region and enters triode region VDS VDS , SAT VGS VTn 0.31V vo ,MIN VDS ,SAT 0.32 V amp 2.5 0.32V = 2.18V Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Maximum Output Amplitude vout(t)= -2.18 V cos(t) vs(t) = 152 mV cos(t) How accurate is the small-signal (linear) model? vs 0.152 0.5 VGS VTn 0.32 Significant error in neglecting third term in expansion of iD = iD (vGS) Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith One-Port Models (EECS 40) A terminal pair across which a voltage and associated current are defined iab vab Circuit Block iab vab Department of EECS iab Rthev vthev vab Rthev ithev University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Two-Port Models iin vin vout We assume that input port is linear and that the amplifier is unilateral: – iout Output depends on input but input is independent of output. Output port : depends linearly on the current and voltage at the input and output ports Unilateral assumption is good as long as “overlap” capacitance is small (MOS) Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Small-Signal Amplifiers Rout Rs vin vs Rin RL Av vin Voltage Amplifier iin is Rs Rin Aii in Rout RL Current Amplifier Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Small-Signal Amplifiers Rs vin vs Rin Gmvin Rout RL Transconductance Amplifier Rout iin is Rs Rin Rmiin RL Transresistance Amplifier Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Common-Source Amplifier (again) How to isolate DC level? Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith DC Bias 5V Neglect all AC signals 2.5 V Choose IBIAS, W/L Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Load-Line Analysis to find Q I RD VDD Vout RD Q slope 5V ID 10k 1 10k 0V ID 10k Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Analysis Rin Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Parameters: Find Rin, Rout, Gm Generic Transconductance Amp Rs vs vin Rin Gmvin RL Rout Rin Gm gm Rout ro || RD Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port CS Model Reattach source and load one-ports: Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Maximize Gain of CS Amp Av gm RD || ro Increase the gm (more current) Increase RD (free? Don’t need to dissipate extra power) Limit: Must keep the device in saturation VDS VDD I D RD VDS , sat For a fixed current, the load resistor can only be chosen so large To have good swing we’d also like to avoid getting too close to saturation Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Source Supply Department of EECS Solution: Use a current source! Current independent of voltage for ideal source University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CS Amp with Current Source Supply Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Load Line for DC Biasing Both the I-source and the transistor are idealized for DC bias analysis Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Two-Port Parameters From current source supply Rin Gm gm Rout ro || roc Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith P-Channel CS Amplifier DC bias: VSG = VDD – VBIAS sets drain current –IDp = ISUP Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Common Gate Amplifier Notice that IOUT must equal -Is DC bias: I SUP I BIAS I DS Gain of transistor tends to hold this node at ss ground: low input impedance load for current input current gain=1 Impedance buffer Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG as a Current Amplifier: Find Ai iout id it Ai 1 Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Input Resistance vgs vt vt vout it gm vgs g mb vt ro Output voltage: v i (r || R ) i (r || R ) out d oc L t oc L At input: vt roc || RL it it gmvt gmb vt r o Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Approximations… We have this messy result g m g mb 1 ro it 1 r || R Rin vt 1 oc L ro But we don’t need that much precision. Let’s start approximating: g m g mb 1 ro roc || RL RL Rin Department of EECS RL 0 ro 1 g m g mb University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Output Resistance vs vs vt g m vgs ( g mb vs ) 0 RS ro 1 1 vt vs gm gmb ro ro RS Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Output Resistance Substituting vs = itRS 1 1 vt it RS gm g mb ro ro RS The output resistance is (vt / it)|| roc Rout Department of EECS ro roc || RS g m ro g mb ro 1 RS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Approximating the CG Rout Rout roc || [ro g m ro RS g mbro RS RS ] The exact result is complicated, so let’s try to make it simpler: g m 500S g mb 50S ro 200k Rout roc || [ro g m ro RS RS ] Assuming the source resistance is less than ro, Rout roc || [ro g m ro RS ] roc || [ro (1 g m RS )] Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CG Two-Port Model Function: a current buffer • Low Input Impedance • High Output Impedance Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Common-Drain Amplifier In the common drain amp, the output is taken from a terminal of which the current is a sensitive function VGS Department of EECS I DS W 1 Cox (VGS VT ) 2 L 2 2 I DS VT W Cox L Weak IDS dependence University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Voltage Gain Note vgs = vt – vout vout g m vgs g mb vout roc || ro vout g m vt vout g mb vout roc || ro Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Voltage Gain (Cont.) vout g m vt vout g mb vout roc || ro KCL at source node: 1 gmb gm vout gmvt roc || ro Voltage gain (for vSB not zero): vout vin gm 1 g mb g m roc || ro vout gm 1 vin g mb g m Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Output Resistance Sum currents at output (source) node: Rout vt ro || roc || it Rout Department of EECS it gmvt g mb vt 1 g m g mb University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CD Output Resistance (Cont.) ro || roc is much larger than the inverses of the transconductances ignore Rout 1 g m g mb Function: a voltage buffer • High Input Impedance • Low Output Impedance Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Voltage and current gain Current tracks input voltage tracks input Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Bias sensitivity When a transistor biasing circuit is designed, it is important to realize that the characteristics of the transistor can vary widely, and that passive components vary significantly also. Biasing circuits must therefore be designed to produce a usable bias without counting on specific values for these components. One example is a BJT base bias in a CE amp. A slight change in the base-emitter voltage makes a very large difference in the quiescent point. The insertion of a resistor at the emitter will improve sensitivity. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Insensitivity to transistor parameters Most of the circuit parameters are independent of variation of the transistor parameters, and depend only on resistance ratios. That is often a design goal, but in integrated circuits we will not want to use so many resistors. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith NMOS pullup Rather than using a big (and expensive) resistor, let’s look at a NMOS transistor as an active pullup +V device vout Note that when the transistor is connected this way, it is not an amplifier, it is a two terminal device. When the gate is connected to the drain of this NMOS device, it will be in saturation, so we get the equation for the drain current: W 2 ID nCox VSG VTn 1 nVSD 2L Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small signal model So we have: W 2 ID n Cox VSG VTn 1 nVSD 2L W W 2 2 C V V 1 V C V V n ox Tn n n ox Tn 2L 2L The N channel MOSFET’s transconductance is: gm iD W nCox VSG VTn 2 W nCox I D vSG L L Q And so the small signal model for this device will be a resistor with a resistance: 1 r gm Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith IV for NMOS pull-up The I-V characteristic of this pull-up device: I D1 W L n Cox VDD VTn 2 VDD Vt 2 I V Department of EECS VDD University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Active Load We can use this as the pullup device for an NMOS common source amplifier: W1 VDD 2 I D1 nCox Vgs1 VTn1 2 L1 W 2 I D 2 2 nCox Vgs 2 VTn 2 2 L2 M2 vin Department of EECS M1 vout V0 VDD Vgs 2 V0 VDD Vt 2 2I 2 nCox W2 / L2 University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Active Load Since I2=I1 we have: V0 VDD Vt 2 VDD And since: M2 vin Department of EECS M1 vout 2 I1 nCox W2 / L2 Vgs1 Vi V0 VDD Vtn1 W1 / L1 V V W2 / L2 i t1 University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Behavior If the output voltage goes higher than one threshold below VDD, transistor 2 goes into cutoff and the amplifier will clip. If the output goes too low, then transistor 1 will fall out of the saturation mode. Within these limitations, this stage gives a good linear amplification. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith CMOS Diode Connected Transistor Department of EECS Short gate/drain of a transistor and pass current through it Since VGS = VDS, the device is in saturation since VDS > VGS-VT Since FET is a square-law (or weaker) device, the I-V curve is very soft compared to PN junction diode University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Diode Equivalent Circuit di RD OUT dvOUT 1 vt it IOUT 0 1 RD gm Equivalent Circuit: RD iOUT + VD +- vOUT - Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith The Integrated “Current Mirror” High Res Low Resis Department of EECS M1 and M2 have the same VGS If we neglect CLM (λ=0), then the drain currents are equal Since λ is small, the currents will nearly mirror one another even if Vout is not equal to VGS1 We say that the current IREF is mirrored into iOUT Notice that the mirror works for small and large signals! University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Mirror as Current Sink The output current of M2 is only weakly dependent on vOUT due to high output resistance of FET M2 acts like a current source to the rest of the circuit Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Small-Signal Resistance of I-Source Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Improved Current Sources Goal: increase roc Approach: look at amplifier output resistance results … to see topologies that boost resistance Rout ro Looks like the output impedance of a commonsource amplifier with source degeneration Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Effect of Source Degeneration vt (it g m vgs )ro vRS vgs vRS 1 Req gm vRS it RS vt (it gm RS it )ro it RS vt Ro 1 g m RS ro it Equivalent resistance loading gate is dominated by the diode resistance … assume this is a small impedance Output impedance is boosted by factor 1 gm RS Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Cascode (or Stacked) Current Source Insight: VGS2 = constant AND VDS2 = constant Small-Signal Resistance roc: Ro 1 gm RS ro Ro 1 gm ro ro Ro g m r02 ro Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Drawback of Cascode I-Source Minimum output voltage to keep both transistors in saturation: V V V OUT , MIN DS 4, MIN DS 2, MIN VDS 2, MIN VGS 2 VT 0 VDSAT 2 iOUT VD 4 VDSAT 2 VGS 4 VGS 2 VGS 4 VT 0 VOUT , MIN VGS 2 VGS 4 VT 0 Department of EECS vOUT University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Sinks and Sources Sink: output current goes to ground Department of EECS Source: output current comes from voltage supply University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Current Mirrors We only need one reference current to set up all the current sources and sinks needed for a multistage amplifier. Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Summary of Cascaded Amplifiers General goals: 1. Boost the gain (except for buffers) 2. Improve frequency response 3. Optimize the input and output resistances: Rin Voltage: Current: Transconductance: Transresistance: Department of EECS 0 0 Rout 0 0 University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Start: Two-Stage Voltage Amplifier • Use two-port models to explore whether the combination “works” CS2 CS1 CS1,2 Results of new 2-port: Rin = Rin1, Rout = Rout2 Av Gm1 Rin 2 || Rout1 Gm2 Rout 2 Av Gm1Gm2 Rin 2 || Rout1 Rout 2 Department of EECS University of California, Berkeley EECS 105 Spring 2004, Lecture 42 Prof. J. S. Smith Cascading stages CS2 CS1 CD3 Input resistance: Voltage gain (2-port parameter): Av gm1 ro1 || roc1 gm2 ro 2 || roc 2 Output resistance: Rout Department of EECS 1 g m g mb University of California, Berkeley