Download B wheel Board Gain Differences

B wheel Board Gain
Differences
Mitch Newcomer
May 5, 2005
Motivation
• Gain differences have been observed for a number of B wheel
boards from ALGEN.
• Smallest Division ASD ASIC
• Typical - Board or DTMROC
Two boards have been examined in detail.
Board Chip
Gain
V656 A0053011(d) Typical
V660 A0156162(d) Low
V660 A0157867
Low
(d) Indicates Chip is oriented below
Silk screen diode symbol.
Penn May 5, 2005
2
External Pulser Response at BLR Output
for two low gain and two typical channels 4fC
CERN 32 channel Pulser
Penn May 5, 2005
3
External Pulser  BLR Monitor Out
Differential Output at Monitor vs External Pulser Input Charge
1000
External Pulser : Standard 32 channel "odd/even"
Diff mV out
Low Gain ASD B wheel board
V0660
Normal Gain ASD B wheel board V0656
100
A053011 (Normal)
A0156162(Low Gain)
10
0.1
1
10
100
Input Charge in fCoul
Penn May 5, 2005
4
Internal Pulser  BLR Monitor Out
Test Pulse DAC Counts
VS Measured Differential Voltage at BLR Monitor
1000
Diff mV
Low Gain ASD B whe e l board
V0660
Normal Gain ASD B whe e l board V0656
100
A0156162(Low Gain)
A0157867 (Low Gain)
A053011(Normal)
10
1
10
100
DAC Counts
Penn May 5, 2005
5
Internal Pulser to 50% DAC threshold
Internal Pulser vs 50% Threshold Difference Values
Referenced to Intenal pulser Data taken at 5 counts
90
Threshold DAC Diff in 50% values
80
70
60
Typical
A0053011
Low Gain A0156162
50
40
30
Range values shown are the difference between
Measured 50% threshold data and 50% threshold
for an internal pulser setting of 5 DAC counts for
each channel shown.
This helps eliminated offsets in data among channels
20
10
0
0
2
4
6
8
10
12
14
16
Difference Test Pulse Value minus 5 DAC counts
Penn May 5, 2005
6
Test Pulse Response at BLR Output
TP Value set to 60 (11fC)
Typical
Low Gain
212mV
159mV
Penn May 5, 2005
7
Test Pulse Input to ASDBLR from
W0223 Triple Jumper Position #8
to Typical and Low Gain ASD
Low and Typical Super imposed
Penn May 5, 2005
8
Preliminary Conclusions
1.
2.
3.
4.
5.
6.
Low Gain Channels are ~10% lower for External pulser and ~25% lower
for the Internal pulser when measured at BLR monitor output.
Gain is constant down to ~1fC. Low Gain channels do not present risk
that BLR will operate in a highly NL range for near threshold signals.
Using the same DTMROC to compare measurements of the whole signal
processing chain indicate only a small gain difference between Low Gain
and Typical ASDBLR boards. Examination of several chips has shown
that the gain difference is relatively constant implying a batch difference.
Pulse shapes observed at the BLR output for low gain and typical chips
are qualitatively the same from 2fC to 80fC of injected charge.
The maximum test pulse range is only about 12fC. Setting the
DTMROC BLR bias resistor to a smaller value would increase this range.
Low Gain and Typical ASD’s exhibit nearly identical test pulse shapes as
observed at the Test pulse input to the ASDBLR.
Penn May 5, 2005
9