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EECS 105 Fall 2003, Lecture 12
Lecture 12:
MOS Transistor Models
Prof. Niknejad
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Lecture Outline

MOS Transistors (4.3 – 4.6)
–
–
Department of EECS
I-V curve (Square-Law Model)
Small Signal Model (Linear Model)
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Observed Behavior: ID-VGS
I DS
I DS
VDS
VGS
VT



VGS
Current zero for negative gate voltage
Current in transistor is very low until the gate
voltage crosses the threshold voltage of device
(same threshold voltage as MOS capacitor)
Current increases rapidly at first and then it finally
reaches a point where it simply increases linearly
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Observed Behavior: ID-VDS
VGS  4V
I DS / k
non-linear resistor region
resistor region
I DS
“constant” current
VDS
VGS  3V
VGS
VGS  2V
VDS



For low values of drain voltage, the device is like a resistor
As the voltage is increases, the resistance behaves non-linearly
and the rate of increase of current slows
Eventually the current stops growing and remains essentially
constant (current source)
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
“Linear” Region Current
VGS  VTn
S
p+
G
D
n+



y
n+
p-type
NMOS
VDS  100mV
x
Inversion layer
“channel”
If the gate is biased above threshold, the surface is
inverted
This inverted region forms a channel that connects
the drain and gate
If a drain voltage is applied positive, electrons will
flow from source to drain
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
MOSFET: Variable Resistor

Notice that in the linear region, the current is
proportional to the voltage
I DS

W
 nCox (VGS  VTn )VDS
L
Can define a voltage-dependent resistor
VDS
1
L
Req 


I DS nCox (VGS  VTn )  W

L

  R (VGS )
W

This is a nice variable resistor, electronically
tunable!
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Finding ID = f (VGS, VDS)

Approximate inversion charge QN(y): drain is
higher than the source  less charge at drain end
of channel
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Inversion Charge at Source/Drain
QN ( y)  QN ( y  0)  QN ( y  L)
QN ( y  0)  Cox (VGS  VTn )
QN ( y  L ) 
 Cox (VGD  VTn )
VGD  VGS  VDS
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Average Inversion Charge
Source End
Drain End
Cox (VGS  VT )  Cox (VGD  VT )
QN ( y )  
2
Cox (VGS  VT )  Cox (VGS  VSD  VT )
QN ( y )  
2
Cox (2VGS  2VT )  CoxVSD
VDS
QN ( y )  
 Cox (VGS  VT 
)
2
2


Charge at drain end is lower since field is lower
Simple approximation: In reality we should
integrate the total charge minus the bulk depletion
charge across the channel
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Drift Velocity and Drain Current
“Long-channel” assumption: use mobility to find v
v( y )   n E ( y )   n (V / y ) 
nVDS
L
Substituting:
VDS
VDS
I D  WvQN  W 
Cox (VGS  VT 
)
L
2
VDS
W
I D   Cox (VGS  VT 
)VDS
L
2
Inverted Parabolas
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Square-Law Characteristics
TRIODE REGION
Boundary: what is ID,SAT?
SATURATION REGION
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
The Saturation Region
When VDS > VGS – VTn, there isn’t any inversion
charge at the drain … according to our simplistic model
Why do curves
flatten out?
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Square-Law Current in Saturation
Current stays at maximum (where VDS = VGS – VTn = VDS,SAT)
VDS
W
I D   Cox (VGS  VT 
)VDS
L
2
I DS , sat 
V V
W
Cox (VGS  VT  GS T )(VGS  VT )
L
2
W Cox
I DS , sat 
(VGS  VT ) 2
L 2
Measurement: ID increases slightly with increasing VDS
model with linear “fudge factor”
I DS , sat
Department of EECS
W Cox

(VGS  VT ) 2 (1  VDS )
L 2
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Pinching the MOS Transistors
VGS  VTn
S
p+
Depletion Region
NMOS




n+
G
D
VGS  VTn
p-type
VDS
n+
Pinch-Off Point
When VDS > VDS,sat, the channel is “pinched” off at drain end (hence the
name “pinch-off region”)
Drain mobile charge goes to zero (region is depleted), the remaining elecric
field is dropped across this high-field depletion region
As the drain voltage is increases further, the pinch off point moves back
towards source
Channel Length Modulation: The effective channel length is thus reduced
 higher IDS
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Linear MOSFET Model
Channel (inversion) charge: neglect reduction at drain
Velocity saturation defines VDS,SAT = Esat L = constant
Drain current:
- vsat / n
I D,SAT  WvQN  W (vsat )[Cox (VGS  VTn )],
|Esat| = 104 V/cm, L = 0.12 m  VDS,SAT = 0.12 V!
I D,SAT  vsatWCox (VGS  VTn )(1  nVDS )
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Why Find an Incremental Model?

Signals of interest in analog ICs are often of the
form:
vGS (t )  VGS  vgs (t )
Fixed Bias Point
Small Signal
Direct substitution into iD = f(vGS, vDS) is
tedious AND doesn’t include charge-storage
effects … pretty rough approximation
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Which Operating Region?
VGS  3V
TRIODE
VDS  3V
SAT
OFF
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Changing One Variable at a Time
I DS / k
Square Law
Saturation
Region
VDS  3V
VT  1V
Linear
Triode
Region
Slope of Tangent: Incremental current increase
VGS
Assumption: VDS > VDS,SAT = VGS – VTn (square law)
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
The Transconductance gm
Defined as the change in drain current due to a change in the
gate-source voltage, with everything else constant
I DS , sat 
gm 
iD
vGS
W Cox
(VGS  VT ) 2 (1  VDS )
L 2

VGS ,VDS
iD
vGS
 Cox
VGS ,VDS
g m   Cox
g m  Cox
W
L
W
(VGS  VT )(1  VDS )
L
W
(VGS  VT )
L
Gate Bias
2 I DS
W
 2Cox I DS
W
L
Cox
L
gm 
Department of EECS
0
2 I DS
(VGS  VT )
Drain Current Bias
Drain Current Bias and
Gate Bias
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Output Resistance ro
Defined as the inverse of the change in drain current due
to a change in the drain-source voltage, with everything
else constant
Non-Zero Slope
 I DS
 VDS
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Evaluating ro
iD 
W Cox
(VGS  VT ) 2 (1  VDS )
L 2
 i
ro   D
 vDS

r0 
VGS ,VDS




1
1
W  Cox
(VGS  VT ) 2 
L 2
1
r0 
 I DS
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Total Small Signal Current
iDS (t )  I DS  ids
iDS
iDS
ids 
vgs 
vds
vgs
vds
1
ids  g m vgs  vds
ro
Transconductance
Department of EECS
Conductance
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Putting Together a Circuit Model
1
ids  g m vgs  vds
ro
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Role of the Substrate Potential
Need not be the source potential, but VB < VS
Effect: changes threshold voltage, which
changes the drain current … substrate acts
like a “backgate”
g mb
iD

vBS
Q
iD

v BS
Q
Q = (VGS, VDS, VBS)
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Backgate Transconductance
VT  VT 0  
Result:
Department of EECS
g mb 
iD
vBS

Q

iD
VTn
Q
VSB  2 p  2 p
VTn
vBS

Q

 gm
2 VBS  2 p
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Four-Terminal Small-Signal Model
1
ids  g m vgs  g mb vbs  vds
ro
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
MOSFET Capacitances in Saturation
Gate-source capacitance: channel charge is not
controlled by drain in saturation.
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Gate-Source Capacitance Cgs
Wedge-shaped charge in saturation  effective area is (2/3)WL
(see H&S 4.5.4 for details)
C gs  (2 / 3)WLC ox  Cov
Overlap capacitance along source edge of gate 
Cov  LDWCox
(Underestimate due to fringing fields)
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Gate-Drain Capacitance Cgd
Not due to change in inversion charge in channel
Overlap capacitance Cov between drain and source
is Cgd
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Junction Capacitances
Prof. A. Niknejad
Drain and source diffusions have (different) junction
capacitances since VSB and VDB = VSB + VDS aren’t
the same
Complete model (without interconnects)
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
P-Channel MOSFET
Measurement of –IDp versus VSD, with VSG as a parameter:
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Square-Law PMOS Characteristics
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
Small-Signal PMOS Model
Department of EECS
University of California, Berkeley
EECS 105 Fall 2003, Lecture 12
Prof. A. Niknejad
MOSFET SPICE Model
Many “levels” … we will use the square-law
“Level 1” model
See H&S 4.6 + Spice refs. on reserve for details.
Department of EECS
University of California, Berkeley