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Delay Evaluation
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Problem Description
Total capacitance model
Interconnect delay
Distributed RC Model
Other complications
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1. Problem Description
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Given a pair of pins, compute pin-to-pin
delay and possibly output waveform
Delay
Cell
Interconnect
Cell
…
Cell
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On-going Research
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Difficulty:
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Non-linear behavior of device
Complex interconnect parasitic
No well-accepted approach
Any new idea are welcome
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Circuit Model
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For an inverter
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Csink
…
Csink
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Sink Capacitance
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Gate capacitance, input
capacitance, pin capacitance
Given for standard cells
Can be found using SPICE
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Apply an AC voltage and
measure current
Average over a range of
frequency
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2. Total Capacitance Model
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Valid for Rd >> Rmetal
All fanouts have the same delay
RC
Rd
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Rd
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Ctotal
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RC Delay
0.35Vdd
Vdd
Rpd
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Driver Resistors
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Pull-up and pull-down resistors are not a
constant. Which value should we choose?
Use SPICE to compute Rpd and Rpd
Ids
Vds
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RC Delay
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Assume constant Rpd,
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 t PDf
0.35Vdd  Vdd exp 
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 R pd (Cout  C p ) 
 1 
t PDf  R pd (Cout  C p ) ln 
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 0.35 
 R pd (Cout  C p )
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Zhuo Li pointed out in
this case Elmore delay
is 35% instead of 50%
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Linear Delay
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Delay is linear in Ctotal
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Rd is pull-up/pull-down resistor, assumed to
be linear
Interconnect R ignored
Common for >0.5um technology
standard cells
Delay = t0+f*Ctotal
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t0: Intrinsic gate delay
f: Load factor
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Non-Linear: K-factor
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Consider input transition
time tr/f
Transition time is signal rising time
rising/falling time from 20% to 80%
K-factor equation
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Delay td=k(tr/f, Ctotal)
Output transition time t’r/f=k’(tr/f, Ctotal)
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K-Factor …
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Synopsis K-factor form:
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Piece-wise-quadratic
For each piece,
a*tr+b*Ctotal+c*tr*Ctotal+d
Obtained from SPICE simulation
Ignore interconnect resistance
shielding
Widely used
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3. Interconnect Delay
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Consider the first moment of H(s):
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H(s)   h(t)e dt   h(t)(1  st  )dt
 st
0
0
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
0
0
  h(t)dt  s  t  h(t)dt    1  m1s  
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First Moment
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Consider h(t) as a probability density
function, then m1 is the mean of h(t):

m1 
t

h(t)dt

0
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The name moment comes from
probability theory
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Mean and Median
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If impulse response h(t) is symmetric
h(t)
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hstep(t)
t
t
m1
m2
Then the mean of impulse response equals
median of step response, which is 50% delay
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Elmore Delay
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Since m1 is easy to compute, Elmore
used m1 as the delay for the RC circuit
It can be shown for RC trees, h(t) is
skewed to the left. Therefore Elmore
delay is always an upper bound on the
50% delay
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Example
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1
1
1
2
1
1
3
1
4
1
1
m1_1= –4, m1_2= –7, m1_3= –8, m1_4= –8
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Application of Elmore Delay
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Good
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Closed form expression, easy to compute
Accuracy is better the ramps
Useful for routing and placement
Bad
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Inaccurate
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For less than 0.25 um technology
Unbalanced RC trees
Driver ignored
Not useful for timing verification
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4. Distributed RC Model
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Metal resistance per unit length is
increasing, while gate output resistance
is decreasing
Portion of delay associated with the
interconnect is increasing
Due to resistance shielding, total
capacitance is an over estimation
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Two Step Approach
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Cell delay + interconnect delay
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Cell delay and waveform is computed
using K-factor
Interconnect delay is computed using
Elmore delay or transfer function
Cell
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Interconnect
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Cell
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Sink Waveform
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Given linear input waveform,
convolution is easy
m
~
h (t)   k ie pit
i1
Cell
Ctotal
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Driving Point Waveform
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Ctotal is inaccurate. Use  load, driving
point waveforms match better
RC
Rd
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Rd
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K-factor for  Load?
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Given C1,R,C2 of a  load, search a
table for linear or piece-wise linear
waveform
Rd
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How to Store Table?
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Use  load, the k-factor table is 4dimensional. Too large!
m
~
p i t
h (t)   k ie
i1
Cell
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Effective Capacitance Method
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Use  load
Use 2-dimensional K-factor table
m
~
p i t
h (t)   k ie
i1
Cell
Ceff
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How to Compute Ceff?
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Basic assumption: there exist an input ramp and Ceff,
such that the driving point waveforms are the same
Match I and Ie on average
Rd
I
Ie
Rd
Ceff
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Iteration
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Assume Ceff=Ctotal
Use f-factor to find transition time trf
Compute current for PI model and
Ceff model
If equal then stop, otherwise compute
new Ceff and go to 2
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5. Other Complications
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Side input
 Delay from x to out is different for different
values on y
 Need characterize for all input combinations
Vdd
x
out
y
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Simultaneous Switching
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Too many cases to consider
Big impact on delay
Vdd
x
out
y
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Transistor Sizing
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Re-sized cells are common
Fast techniques to derive k-factor for resized transistors
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Readings on Delay Evaluation
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J. Rubinstein, P. Penfield Jr., and M. A. Horowitz,
“signal delay in RC tree networks,” IEEE Trans. CAD,
1983
F. Dartu, et al., “A gate delay model for high-speed
CMOS circuits,” Proc. ICCAD 1994.
L. C. Chen, et al., “A new gate delay model for
simultaneous switching and its applications,”, Proc.
DAC, 2001.
E. Acar, et al., “TETA: Transistor-level waveform
evaluation for timing analysis,” IEEE Trans. CAD,
2002.
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