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Electrical Characteristics of IC’s
Tri-states
Logic Families
Propagation Delay
Last Edit: January 2011
Paul R. Godin
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Introduction
• Study of Digital Electronics is interesting; as knowledge in the
field increases, learners realize that they can start applying
digital logic designs to create useful and interesting devices.
• The best logic designs, however, will fail without a foundation in
the electrical and other physical properties of logic devices.
What good is a portable design if the batteries drain to quickly,
if components regularly fail or if the prototype doesn’t function
as designed.
• This group of presentations investigate the electrical and
physical properties of digital logic devices, and discusses
practical approaches to logic design.
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Basic Principles
There are many basic principles that guide the electrical
aspects of logic design
Following is a listing of the more common, basic errors
that ENTs make in second semester.
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•
Basic Principle 1
Never allow a gate input to float.
–
A floating input creates a situation where a logic gate can:
• Not perform as expected
• Be damaged by static discharge
• Operate erratically (often difficult to troubleshoot)
• Oscillate (likely to cause problems to other parts of the circuit)
•
Even unused gates in an IC should be tied to logic high or low.
•
Proper switch configuration avoids floating inputs.
Vcc
Vcc
Float
1
0
0
1
Poor Switch Config
Good Switch Config
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Basic Principle 2
• Over-voltage, wrong polarity and negative voltage
damages ICs.
– Ensure voltages are set and checked before connecting to the ICs.
• Mixing Vcc and GND is usually fatal for the device
• In some cases the ICs may continue to function but their performance
and lifespan will be unsure.
+
Vcc
X
-
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Basic Principle 3
• Never tie active outputs together (called a “wired-OR”),
or to Vcc, or to GND.
– This will likely damage certain families and types of devices.
• Leave unused outputs disconnected
• Use the appropriate logic gate to connect outputs together
Vcc
X
X
(unless open collector with
PU resistor)
Examples of Wired-OR
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Basic Principle 4
• Do not use resistors for Vcc input.
– The resistor will drop voltage and the device will not receive adequate voltage.
• The connections for Vcc and Ground must have low resistance
Vcc
X
Examples of an error with Vcc
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Basic Principle 5
• When electrically connecting separate circuits, ensure
there is a common reference (ground in most cases)
– Without a common reference the communication link between the two
separate circuits will be unreliable.
Vcc 1
Vcc 2
Same reference
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Basic Principle 6
• Do not power an IC with the output of another IC.
– The IC’s gate cannot supply enough current or voltage to the load.
• Do not use the power input of an IC as an enable/disable.
– Use steering gates to enable or disable a device’s output.
Vcc
Vcc
X
X
Vcc
Examples of errors by powering a chip
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Other Basic Principles
• More will be added to this list
• This presentation series on electrical issues will address additional
basic principles to designing digital electronics circuits.
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Tri-State Devices
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Logic States
1
0
A
What is the logic state at point A?
What is the logic state of just a piece of wire?
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A 3rd Logic State?
• Digital logic has 2 logic states:
– ‘0’, or low, representing ground, or zero volts
– ‘1’, or high, representing Vcc, or full operational voltage
• Digital logic has 2 dynamic states:
– ‘0’ to ‘1’ transition
– ‘1’ to ‘0’ transition
• In some cases, connection to a common conductor, such as a
BUS, is required. In these cases, we cannot connect two or
more standard outputs together. The results will be short
circuits, half voltages and unpredictable outcomes.
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Tri-States
• A Tri-State buffer (or a 3-state buffer) utilizes a second input to
electrically disconnect the output.
• The third state is called “high impedance”, or simply “Z”.
• The control input is often labeled “OE”, or Output Enable.
A
OE
Y
A
OE
Y
0
1
0
1
1
1
X
0
Z
Status
Enabled (A to Y)
Disabled (high Z)
IEEE/ANSI Symbol for Tri-State
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Tri-State Bus
In this example, several device
outputs share the common
bus. The control system is
designed to allow only 1 device
to be connected to the bus; all
other devices are tri-stated.
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Using Tri-State Devices
• “Tri-stated” is the term used to describe an output from a tristate device that is in the high impedance state.
• Tri-states should be used cautiously…never allow a gate input to
float.
A
B
X
OE
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IC Families
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IC Complexity Designation
• SSI: Small Scale Integration. Usually refers to IC’s that contain
individual gates or flip-flops.
• MSI: Medium Scale Integration. Usually refers to IC’s that contain
counters, shift registers, etc…
• LSI and VLSI: Large and Very Large Scale Integration. Refers to IC’s
that can perform large logic functions.
• ULSI and GSI: Ultra Large Scale Integration and Giga Scale
Integration. ICs with greater than 100,000 and 1 million gates.
• ASIC: Application Specific IC. Refers to IC’s that are custom built
for specific functions, and are vendor-specific. For instance, a T.V.
remote control may contain a single IC that is ASIC.
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Logic Families
• Logic families are devices that share the same electrical and
other performance properties.
• Texas Instruments lists over 40 logic families. Examples
include:
– ACT: Advanced CMOS Technology combines low power with high
output drive current capabilities, and is TTL-compatable.
– CBT: CrossBar technology can function at 5V and 3.3V, and has a
very low propagation delay. Used in bus application.
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Families of IC’s
• There are large varieties of IC families to cover a multitude of
electronics applications, such as:
–
–
–
–
Low voltage
Very low current
High speed
Etc…
• The most common major families include:
– TTL (Transistor-Transistor Logic)
– CMOS (Complimentary Metal Oxide Semiconductor)
• See manufacturer’s web sites for more details…
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Major Family Characteristics
• TTL:
–
–
–
–
–
Transistor-based
Generally faster than CMOS
Larger current carrying capability
Much higher power consumption
Rigid voltage requirements
• CMOS:
–
–
–
–
–
MOSFET-based
Greater noise immunity
Low power consumption
Variable voltage requirements
Low speed (although this continues to be improved)
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Designations-Basic TTL
• The TTL product family usually has a designating part number
that begins with 74xxx.
• Designators may include:
–
–
–
–
S (Schottky-higher switching speeds)
L (Low power)
A (Advanced-improved technology)
F (Fast)
Schmitt
• Example:
– 74LS00 is a Low Power, Shottky device.
Schottky
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Designations-Basic CMOS
• The CMOS product family usually has a designating part number that
begins with 14xxx, 4xxx or 74Cxxx.
• Designators may include:
–
–
–
–
–
B (B-series - more advanced)
U (Unbuffered)
C (metal gate, CMOS)
H (High speed)
T (TTL compatible inputs)
• Example:
– 4011B is a CMOS, Advanced design device
– 74C00 is a CMOS device with a gate layout similar to its TTL counterpart
• CMOS has special handling considerations. See the technical
documents available from the manufacturers.
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Exercise
From TI’s web site (http://focus.ti.com/logic/docs/logicportal.tsp?templateId=598),
determine the special characteristics of the following logic
families:
FB
AHCT
LVT
AUC
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Timing Measurements
• Timing is a critical issue in digital electronics. Much of the
specification sheet for logic devices is devoted to timing
specifications.
• Different families of devices require different measurements.
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Waveform Measurement
Period (T)
Pulse Separation (Ps)
Pulse Width (Pw)
90%
Amplitude
50%
10%
Rise Time (tR)
Fall Time (tF)
Rise and fall times are typically
measured in nanoseconds (ηs)
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Typical Waveform
• Due to the effects of inductance, capacitance, noise, grounding,
device properties and other factors, digital signals tend to be
electrically and timely less than perfect. These effects are
increased with frequency.
Over-shoot
Ringing
Pre-shoot
Droop
Typical Waveform
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Timing problems cause glitches in Asynchronous counters
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
000
100
010
000
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Propagation Delay
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Propagation Delay
• Propagation Delay is defined as the amount of time it takes
after an input signal is applied for the output to change.
• Propagation Delay is caused by:
– Electron Speed in the medium
– Capacitance
• Propagation delay is usually measured in seconds
• Prop Delay varies by logic Family
A
B
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Propagation Delay
• Propagation delay specifications state the direction of the output
pulse edge.
TpLH: Time Low to High change in output
TpHL: Time High to Low change in output
• Prop delay measurements are different for CMOS and TTL devices.
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Propagation Delay
CMOS measured at 50% mark
TTL measured at 1.5 Volt mark
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Propagation Delay
• Typical propagation delays:
– TTL (7400)
• TpLH: 11s typical, 22s maximum
• TpHL: 7s typical, 15s maximum
– TTL (74S00)
• TpLH: 3s typical, 4.5s maximum
• TpHL: 3s typical, 5s maximum
– CMOS (4011B)
• TpLH: 125s typical, 250s maximum
• TpHL: 125s typical, 250s maximum
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Propagation Delay
• Propagation Delay in a circuit is the sum of all the propagation
delays in the output path.
• Always use the worst-case when designing. This means two
calculations; one for each transition.
• The propagation delay value is based on the OUTPUT direction.
• Different manufactures may use the same device number but
may have different specifications.
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Example 1
• Determine the propagation delay for the following circuit,
assuming TpLH: 11s typical, 22s maximum and TpHL: 7s
typical, 15s maximum.
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Example 1 solution
• Total Delay
• TpLH + TpHL + TpLH = 22s + 15s + 22s = 59s
• TpHL + TpLH + TpHL= 15s + 22s + 15s = 52s
• Total Propagation Delay is 59s
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Example 2
• Determine the propagation delay for the following circuit,
assuming TpLH: 11s typical, 20s maximum and TpHL: 7s
typical, 12s maximum.
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Example 2 solution
• Total Delay
• TpLH + TpHL + TpHL = 20s + 12s + 12s = 44s
• TpHL + TpLH + TpLH= 12s + 20s + 20s = 52s
• Total Propagation Delay is 52s
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Exercise 1
• Use the Texas Instruments specification sheet to determine the
propagation delay of the following circuit:
SN74LS04N
SN74S32
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Exercise 2
• Use the Texas Instruments specification sheet to determine the
propagation delay of the following circuit:
CD4049UB
SN74HC32
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End Section 1
©Paul R. Godin
prgodin @ gmail.com
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