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AT91SAM9 Hardware Design considerations
AT91SAM9 Hardware Design
Considerations
Patrick Filippi,
AT91 Beginner Training October 2007, Rousset
AT91SAM9 Hardware Design considerations
Power Supply
 AT91SAM9260  7 Power Supply Rails
 AT91SAM9261  6 Power Supply Rails
 AT91SAM9263  8 Power Supply Rails
 Digital Cells
 VDDCORE,
 VDDIOM, VDDIOP
 VDDBU (Backed-up Regs, POR...)
 Analog Cells
 VDDOSC,
 VDDPLL,
 VDDBU (32KHz OSC.),
 VDDANA
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AT91SAM9 Hardware Design considerations
Power Supply Rails Description
 VDDCORE Pins:
 Power the ARM Core, the Peripherals (SPI, USART,...) and the Internal
SRAM, ROM
 VDDIOM(emory) Pins:
 Power the I/O lines of the External Bus Interface (VDDIOM0, VDDIOM1)
 VDDIOP(eripheral) Pins:
 VDDIOP0: Power the I/O lines (Peripherals I/O‘s) and USB transceivers
 VDDIOP1: Power the I/O lines dedicated to the Camera Interface
 VDDB(ackup)U(nit) Pins:
 Power the 32KHz slow clock oscillator and a part of the system controller
 VDDOSC(illator) Pins:
 Power the Main Oscillator (3 – 20MHz)
 VDDPLL Pins:
 Power the Phase-Locked Loop
 VDDANA(log) Pins:
 Power the Analog to Digital Converter
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AT91SAM9 Hardware Design considerations
Example with the AT91SAM9263
VDDOSC
Main
OSC
VDDPLL
VDDCORE
PLL
ARM926-EJS
VDDIOP 0
AC97
PWM
CAN
USB Host
Transceiver
MCI
USART
UART
USB Device
Transceiver
LCD
Timer
EMAC
HDM
HDP
DM
DP
VDDCORE
XIN XOUT
SRAM
ROM
SPI
POR
TWI
PB1/
AC97/
TK0
P
I
O
SSC
RSTC
POR
PD3/
RXD2/
NPCS3
PIO
SHWDC
32K OSC
GPBREG
RTT
RTT
2-D
Accelerator
Image
Sensor Interface
EBI 0
PIO
EBI 1
A12
XIN32
XOUT32
VDDBU
VDDIOP 1
VDDIOM 1
ISI_D0
ISI_D1
VDDIOM 0
D6
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AT91SAM9 Hardware Design considerations
Flexible Power Supply System
 VDDIO M0 & M1 : 1.65v to 3.6v Range
 One rail can be used for slow 1.8v memories/peripherals (66MHz)
 One rail can be used for fast 3.3v memories/peripherals (100MHz)
 VDDIO P0 & P1:
 VDDIOP0: 3.0v to 3.6v Range for Hi-Speed Peripherals
 VDDIOP1: 1.65v to 3.6v Range for Hi & Low-Speed Peripherals
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AT91SAM9 Hardware Design considerations
Power Supply Decoupling / Bypass
Decoupling Capacitors are application dependent !
 Must be computed according to:
 Maximum allowable ripple voltage on VDDx
 Maximum current (Switching current)
 Frequency to by-pass
How to Compute it ? 
C  1 V .I max .t
CC
Where C is the decoupling capacitor value,
 VCC : the ripple voltage
 I max : the maximum current consumption

t
: the transient time while CMOS is consuming.
Ex. 32 IOs (8mA per IO) , VCC 50mv,
t
IO switching time ~ 1ns
C = ( 1/50mv ) * 32 * 8mA * 1ns ~ 5nF
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AT91SAM9 Hardware Design considerations
Power Supply (Misc.)
 No power supply sequencing required.
 During startup core supply voltage (VDDCORE) slope must be
superior or equal to 5V/ms (related to BMS, OSCSEL errata)
 Ground pins for Digital and Analog Cells are separated
 Maximum Power consumption on VDDCORE with processor
running full-performance algorithm out of high speed memories
(typical VDD and Temp Conditions)
 AT91SAM9260: 100mA
 AT91SAM9261: 50mA
 AT91SAM9263: 70mA
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AT91SAM9 Hardware Design considerations
Choosing a Crystal
 Crystal must be choosen according to the internal load
capacitance of the on-chip oscillator
 Computation example given in the corresponding Schematic
Check List Application note.
http://www.atmel.com/dyn/products/app_notes.asp?family_id=605
then to “Design Considerations“ Section
 More information in the following Application Note.
http://www.atmel.com/dyn/resources/prod_documents/DOC1740.PDF
 Important data to take care of when choosing a crystal (Cf.
Electrical Characteristics)
 Drive Level (Pon in µW)
- Pon Xtal >= Pon Oscillator
 ESR (Equivalent Series Resistor Rs)
- crystal nominal frequency dependent
 CM Motional Capacitance
 CS Shunt Capacitance
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AT91SAM9 Hardware Design considerations
Crystal Oscillator Layout
AT91 Oscillators are low power (< 1mA @20MHz)
... BUT ...
Sensitive to coupling with high-speed signals and high-drive pads
NO HIGH-SPEED SIGNALS ALLOWED UNDERNEATH THE CRYSTAL
Design Example given in the following FAQ
http://support.atmel.no/bin/customer?custSessionKey=&customerLang=en&
noCookies=true&action=viewKbEntry&id=150
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AT91SAM9 Hardware Design considerations
SDRAM Design Ressources
 16-bit and 32-bit SDRAM Connection
 SDRAM Signal Routing Considerations
 SDRAM Performance
“Using SDRAM on AT91SAM9 Microcontrollers”
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AT91SAM9 Hardware Design considerations
GPIOs
Reminders...
 Tolerant IOs:
 The IO can accept a voltage on its input more than its power
supply (Ex. VDDIO = 3.3v , Vinput = 5V)
 Voutput Max. = VDDIO
 Compliant IOs:
 Vinput = Voutput = VDDIO
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AT91SAM9 Hardware Design considerations
GPIOs
 Isource Current:
 This is the current that the GPIO can provide when outputing
a high level. Given as Output Current (Io) in the datasheet.
Can be from 2mA to 16mA according to the product.
 Isink Current:
 This is the current that the IO can accept when outputing a
low level. Same as the output current
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AT91SAM9 Hardware Design considerations
Signal Integrity
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AT91SAM9 Hardware Design considerations
Edge vs. Frequency
 The frequency is not the Devil
 The abruptness of the edge is the “bad boy”
 The spectrum spread is due to edge time and NOT THE
FREQUENCY
“A 100MHz signal with 2ns edges is better than a 66MHz with
0.5 ns edges !”
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AT91SAM9 Hardware Design considerations
Consequences of having fast edges
The Receiver must be very close to the Driver
 “Mechanical” Problems
 Adds constraints in device placement on the board
 Adds constraints in board inter-connect
 Adds constraints in cabling between boards
 Signal Integrity Problems if the device is not close enough
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AT91SAM9 Hardware Design considerations
Electrical Problems
 Signal Reflection between a driver and a receiver
 Generate ringing noise (overshoot & undershoot)
 Increase EMI level
 Reduce I/O lifetime
 May trigger false switching
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AT91SAM9 Hardware Design considerations
What to Check ?
 Reflection will appear if:
 3 x Tpd x Trace Length < Trise (or Tfall)
With
Tpd: propagation time of the signal in the PCB Trace
Trise: Rising Time of the Driver
Ex:
Tr = 1ns
Tpd = 240ps / in
Maximum Trace Length is 1.5 in !
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AT91SAM9 Hardware Design considerations
What to Do ?
 Impedance Matching between the Driver, the PCB Trace
and the Receiver
Driver with
R0 = 10 ohms
Receiver
Zin = 10M Ohm
PCB Trace
Z0 = 50 omhs
Serie termination scheme
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AT91SAM9 Hardware Design considerations
Rise Time and Output Impedance for the AT91 ?
 Input/Output Buffer Information Specification Models (IBIS)
Rising and
Falling Times
 Hyperlynx Visual IBIS Editor (Freeware)
http://www.mentor.com/products/pcb/analysis_verification/hyperlynx/index.cfm
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AT91SAM9 Hardware Design considerations
Rise Time and Output Impedance for the AT91 ?
 Extracting the output Impedance of the driver
PullDown
Data
Delta I
Delta V
Driver’s output
Impedance
Zo = Delta V / Delta I
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AT91SAM9 Hardware Design considerations
AT91SAM9260
 High Drive Pads (16mA)
 Fast Edges 0.6ns
 Output Impedance 7 ohms
Take Care to Simultaneous Switching Noise Problems !
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AT91SAM9 Hardware Design considerations
Simultaneous Switching Noise (SSN)
(Ground Bounce)
 The WORST ENEMY for signal integrity at device or
application level
 Example:
With 20pf per pin, with a 32-bit data bus, it has to switch
from 3.3V to 0v in 1nS => I = 1A !!! Just during the transition
Toggling Output
Ground
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AT91SAM9 Hardware Design considerations
Simultaneous Switching Noise (SSN)
 Pay attention to local decoupling of VDDx pins of the chip
for corresponding IOs used.
 Robust Analogue Ground and Digital Ground Decoupling
 Series termination will also help in reducing the ground
bounce voltage level (slower outputs)
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AT91SAM9 Hardware Design considerations
Riddle !
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AT91SAM9 Hardware Design considerations
This is the Problem !
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AT91SAM9 Hardware Design considerations
Oscilloscope Input Model
 A typical X10 probe has an equivalent input impedance
consisting of a 10 M resistance in parallel with a
10/15pF capacitor.
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AT91SAM9 Hardware Design considerations
The Inductance of the ground loop is the weak point
 With a quick analysis:
 We have Cprobe =12 pF , the probe input capacitance
 We have a 16 cm long ground link with 1.25 µH/m
(therefore , Lprobe=200 nH inductance).
 We have a very low serial resistor (approximately, it’s about
30 ohms for our CMOS output gates) vs. a Lprobe, Cprobe
lower impedance (imaginary part)
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AT91SAM9 Hardware Design considerations
Experimental Data
 With our measurement and the computed data, we are
able to calculate the resonance frequency of the system:
 F=1/(2*pi*(Lprobe* Cprobe)1/2) = 103 MHz
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