Download Broadband Data Signals & Circuits

Advantages of Using CMOS
• Compact (shared diffusion regions)
• Very low static power dissipation
• High noise margin (nearly ideal inverter voltage transfer characteristic)
• Very well modeled and characterized
• Mechanically robust
• Lends itself very well to high integration levels
• “Analog” CMOS process usually includes non-salicided poly layer for
linear resistors.
• SiGe BiCMOS is very useful but is a generation behind currently
available standard CMOS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
1
Transistor fT Calculation
VDD
ig
id
vgs
fT is the frequency at which
gm = mCox
Cgs
W
VGS -Vt
L
(
)
Cgs = gWLCox
VGS
id
gm
=
becomes
i g 2pfTCgs
wT = 2pfT =
1.
m
V -Vt )
2 ( GS
gL
fT gives a fundamental speed measure of a technology.
0.25 µm CMOS: fT ~ 23GHz (VDD = 2.5V)
0.18 µm CMOS: fT ~ 57GHz (VDD = 1.8V)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
2
Static CMOS propagation delay:
Wp
Lp
Vout
Vin
Wn
Ln
t fall »
Wp
Lp
Wn
Ln
CL
mn
Wn
VDD -Vt
Ln
(
CL
t rise »
)
mp
Wp
Lp
(V
DD
-Vt
)
Assume: Wp = 3Wn for optimum noise margin.
Lp = Ln = Lmin
t rise = t fall =
gLmin (Wp +Wn )Cox
mnCox
gL2min
=
mn
Wn
(VDD -Vt )
Lmin
æ W ö
1
4
=
çç1+ p ÷÷
è Wn ø VDD -Vt wT
Operation is 4X slower than theoretical
maximum due to n-channel & p-channel
gates connected in parallel.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
(Actual  values will be higher
due to high diffusion
capacitances present in submicron transistors.)
3
Verifying with simulation:
n-channel ac simulation
to determine fT:
CMOS inverter transient simulation:
IG
Vin
Vout
ID
fT = 57GHz
EECS 270C / Winter 2014
t = 18ps »
Prof. M. Green / U.C. Irvine
6.4
wT
4
Single-Ended Signaling in CMOS
VDD
Vin
IDD
Vin
Vout
Vout
ISS
ISS
sub
IDD
VSS
Series R & L cause supply/ground bounce.
Resulting modulation of transistor Vt’s result in pattern-dependent jitter.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
5
Effect of Supply/Ground Bounce on Jitter
VDD
¢
data in
data out
clock in
clock out
VSS
¢
Rs = 5 Ls = 5nH
VDD
¢
clock out
Rs = 0
Ls = 0
VSS
¢
clock out
Rs = 5
Ls = 5nH
EECS 270C / Winter 2014
data out
Prof. M. Green / U.C. Irvine
6
Summary of CMOS Gate Performance
Advantages of static CMOS gates:
1.
2.
3.
Simple & straightforward design.
Robust operation.
Nearly zero static power dissipation.
Disdvantages of static CMOS gates:
1.
2.
3.
Full speed of transistors not exploited due to n-channel & pchannel gate in parallel at load.
Single-ended operation causes current spikes leading to
VDD/VSS bounce.
Single-ended operation also highly sensitive to VDD/VSS bounce
leading to jitter.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
7
Current-Mode Logic (CML)
CML inverter:
VDD
R
R
Vout+
• Based on conventional differential pair
Vout-
CL
• Differential operation
CL
Vin+
Vin-
ISS
EECS 270C / Winter 2014
• Inherent common-mode rejection
• Very robust in the presence of commonmode disturbances (e.g., VDD / VSS bounce)
Prof. M. Green / U.C. Irvine
8
DC Biasing of CML Inverter
VDD
1
ISS R
2_
1
ISS R
2 _
VOUT(DC )
VOUT(DC )
R
VIN(DC )
+
W
L
VGS _
1
Vin(DC ) =Vout (DC ) =VDD - ISS R
2
+
+
W
L
VS
_
ISS
VBIAS
EECS 270C / Winter 2014
R
To keep current source transistor in saturation:
VIN(DC )
+
VGS
VS > VBIAS -Vt
VS =Vin(DC ) -VGS
Vin(DC) > VBIAS + (VGS -Vt )
Prof. M. Green / U.C. Irvine
9
Logic Swing & Gain of CML Inverter
Vhigh =VDD
Vlow =VDD - ISS R
VDD
R
R
VDD-ISSR
ISS
VDD
CL
Vswing = ISS R
VDD
0
CL
W
L
W
L
ISS
To achieve full current switching:
VDD-ISSR
(
Vswing ³ VGS -Vt
Vswing
Vmin
Vswing
Vmin
EECS 270C / Winter 2014
=R
)
|I D =ISS
=
2ISS
mnC
W
ox L
ºVmin
1
W
mCox ISS
2
L
> 1 for correct operation
Prof. M. Green / U.C. Irvine
10
Small-Signal Behavior of CML Inverter
Small-signal voltage gain:
Av = gm R = R mCox
Recall
Vswing
Vswing
Vmin
Vmin
=
=R
Av
2
EECS 270C / Winter 2014
rise/fall time constant:
W
L SS
I
1
W
mCox ISS > 1
2
L
t = RCL (Assuming fanout of 1)
CL = gCoxWL
t = R(gWLCox )
Av ³ 2
for full switching
Note: rising & falling
time constants are the same
Prof. M. Green / U.C. Irvine
11
Speed vs. Gain in Logic Circuits
fast input transition:
step response determined by 
slow input transition:
step response determined by Av
Largest possible gain-bandwidth product is desirable.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
12
Relationship between Av ,  , and Vswing
Av = R mnCox
Av2 = mnCox
W
L SS
I
W
m
ISSR2 = n2 × RgWLCox × ISSR
L
gL
(
)(
t
mn
= 2 Vswing
t
gL
Av2
)
Vswing
mn
A = 2 × t × Vswing
gL
2
v
“large-signal” gain-bandwidth product
Larger logic swing preferred for higher gain-bandwidth product
Larger Vswing  Larger Vmin  smaller W/L  larger current density
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
13
Thought Experiment
R
R
R
R
W
L
W
L
W
L
W
L
ISS
ISS
Suppose we decrease current density by increasing W/L:
W
1
´ 2 Þ Vmin ´
, CL ´ 2
L
2
R´
1
t = RC ´ 2
Slower!
2
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
14
Note that the load is only one gate capacitance:
t = RCL = R
gm
wT
=
Av
wT
»
2
CML speed ~ 2.5 times faster than static CMOS
wT
n-channel ac simulation
to determine fT:
CML buffer transient simulation:
IG
ID
t = 8ps »
2.9
wT
fT = 57GHz
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
15
Typical Vswing: 0.3 ×VDD
• Should be large enough to allow sufficient gain-bandwidth product.
• Should be small enough to prevent transistors from going into triode.
* CML will still work in triode (unlike BJT), but there is no additional
speed benefit.
Vswing = ISS R
Once Vswing has been chosen, designer can trade off between gain &
bandwidth by parameterizing between R & ISS:
t = R(gWLCox )
Higher speed: ISS
R
Av = R mCox
Higher gain:
R
EECS 270C / Winter 2014
W
L SS
I
Prof. M. Green / U.C. Irvine
ISS
16
Other Benefits of CML Gates
1.
Constant current bias  VDD / VSS bounce greatly reduced
ISS
KCL sets this current to be nearly constant.
ISS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
17
VDD
¢
data in
data out
clock in
clock out
VSS
¢
Rs = 5 Ls = 5nH
clock out
VDD
¢
Rs = 0
Ls = 0
VSS
¢
clock out
Rs = 5
Ls = 5nH
EECS 270C / Winter 2014
data out
Prof. M. Green / U.C. Irvine
18
2. Non-inverting buffer available without additional delay:
CMOS:
tp
2tp
inverter
buffer
CML:
Vout+
Vout -
Vout- Vout+
Vin-
Vin+
buffer
inverter
EECS 270C / Winter 2014
Vin-
Vin+
Prof. M. Green / U.C. Irvine
19
Fanout & Scaling of CML Gates
R
Vout-
1x
=
Vin+
W
L
R
Vout+
W
L
Vin-
ISS
R/n
Vout-
R/n
Vout+
W
L
W
n´
L
nx
=
Vin+
n´
Vin-
All voltages unchanged from unit-sized buffer.
Currents & power increase by factor of n.
nISS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
20
For fanout of n:
t = nCL R
Av2
t
=
2m
V
2 swing
ngL
 increases linearly with fanout.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
21
From interconnect, etc.; assumed not to scale with buffer sizes
æ C ö
t = nCL +Cp × R / n = gWLCox R × çç1+ p ÷÷
è nCL ø
(
)(
A = 2mnC
nW
ox L
2
v
(
)
)(
)
nISS × R / n
2
-1
æ
ö
C
A
2m
p
÷÷
= 2n Vswing × çç1+
t
gL
è nCL ø
= 2mnCox
W
L SS
I R2
2
v
(
)
Should set n » 0.1× Cp / CL to minimize
degradation due to interconnect capacitance
Power (proportional to n) determined primarily by interconnect capacitance!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
22
Sub-micron MOSFETs obey square-law characteristics only in a limited region!
ID
ID
Mobility reduction (linear)
+
VGS _
Square-law behavior
Weak inversion (exponential)
VGS
CML buffer design procedure:
1.
Determine largest allowable ISS (usually limited by electromigration constraints)
2.
Choose “unit-sized” n-channel transistor (typically W/L=20)
3.
Run a series of simulations to determine optimum value of R:
R too small: full current switching not achieved
R too large: slower than necessary
4.
Choose minimum scaling factor after laying out some test buffers of various
sizes and determining approximate value of interconnect capacitance Cp.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
23
1. Determine largest allowable ISS
standard layout
shared drain
(1/2 diffusion capacitance)
ID £ I max
Imax independent of W
determined by electromigration limits
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
24
CML Design Procedure
Example
Choose: ISS = 400mA
R = 900
ISSR = 360mV
tp = 10ps
R too small
W
4 mm
=
L 0.18 mm
R = 1200
ISSR = 480mV
tp = 12ps
*R optimum*
R = 1500
ISSR = 600mV
tp = 14ps
R too large
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
25
Parameterizing Between Gain & Bandwidth
ISS = 100 µA
R = 4.8 k
Av = 9.3 dB
BW = 2.6 GHz
ISS = 200 µA
R = 2.4 k
Av = 7.1 dB
BW = 5.5 GHz
ISS = 400 µA
R = 1.2 k
Av = 3.9 dB
BW = 11.5 GHz
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
26
Parameterized CML Buffer
R·
GBW
GSCALE · MSCALE
W
· GSCALE · MSCALE
L
ISS ·
GSCALE · MSCALE
GBW
GSCALE: Global scaling parameter
(depends on Cp)
MSCALE: Local scaling parameter
(depends on fanout or bit rate)
GBW:
Gain-bandwidth parameter
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
27
CML with p-channel Active Load
Can be used if linear resistors
are not available.
p-channel load transistors operates in triode region:
Increased capacitance and mismatch result
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
28
Capacitance Comparison (1)
Poly resistor:
p-channel MOSFET:
1
C » Cpoly -sub
2
1
C » Cdepletion + Cchannel -gate + Cchannel -sub
2
(
)
gate
channel
sub
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
29
Capacitance Comparison (2)
(Numbers based on TSMC 180nm CMOS process)
Cpoly-sub  Cchannel-sub : 0.13 fF/ m2
Cdepletion : 1.20 fF/ m2
Cchannel-gate : 7.80 fF/ m2
1
C » Cpoly -sub
2
= 0.1 fF
Poly resistor: Wpoly = 0.6
Lpoly = 2.5
p-channel MOSFET:
Wchannel = Wdiff = 2.5 µm
Lchannel = 0.18 µm
Ldiff = 0.3 µm
C » Cdepletion +
=
EECS 270C / Winter 2014
0.9 fF
(
)
1
Cchannel -gate + Cchannel -sub
2
+ 1.8 fF + .03 fF
= 2.8 fF
Prof. M. Green / U.C. Irvine
30
Capacitance Comparison (3)
R = 1.2 k
s = 235  
Wr = 0.6 µm
Lr = 2.5 µm
Cres = 0.1 fF
M1
Wp = 2.5 µm
Ldiff = 0.3 µm
Cd2 = 2.8 fF
M1
M2
M2
M1
M1
Cd1 = 3.7 fF
Cg1 = 5.8 fF
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
31
Pulse Response Comparison
PWin = 100ps
resistor load
R = 1.2 k
td = 16 ps; PWout = 100 ps
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
p-channel load
(W/L)p = 2.5 µm / 0.18 µm
td = 20 ps; PWout = 98 ps
32
Eye Diagram Comparison
including mismatch effects
resistor load
sR
R
p-channel load
s ID
= 1.5% mismatch
ID
= 4% mismatch
160mV gate-referred mismatch
DCD
ISI
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
33
Series-Gated CML Topology
XOR gate:
MA
MA
MA
MB
MA
MB
Common-mode voltage of BP/N critical:
• Too low  current source transistor biased in triode
• Too high  Transistors MB biased in triode
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
34
Series-Gated CML (2)
VS
I1
BP
I2
BN
VBP -VBN
I1 - I2
ISS
Transistors should be biased in saturation
to realize maximum gm .
VBP -VBN
Slope = gm
Especially important when gate voltages exhibit
slow slew rates
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
-ISS
35
IBP - IBN
VB(cm) = 1.0
VB(cm) = 1.3
VB(cm) = 1.6
DC current:
IBP - IBN
VB(cm) = 1.3
VB(cm) = 1.0
VBP -VBN
Transient response:
(400mV amplitude sine
wave applied to BP/BN)
VB(cm) = 1.6
t
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
36
Level-Shifting CML Buffer
Used to drive clock inputs
of series-gated CML gates
VDD
Output levels:
+
ISS Rcm
_
Vlow
R
(
= (V
)
) -I
Vhigh = VDD - ISSRcm
Rcm
DD
- ISSRcm
SS
R
Vswing = ISSR
ISS
• DC levels shifted down by ISSRcm
• Vswing unchanged
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
37
R
CML Select Circuit
Be reassigning the inputs, the XOR can be transformed into a Select
circuit. Used in a 2:1 multiplexer.
R
SELA
R
OUTP
OUTN
AP
AN
BP
SELA
BN
SELB
ISS
EECS 270C / Winter 2014
AP/N
BP/N
OUTP/N
Prof. M. Green / U.C. Irvine
38
CML Latch
By setting BP/N = OUTP/N, we can construct a CML latch:
OUTP
OUTN
DP
DN
CKP
CKN
ISS
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
39
CML D Flip-Flop
XP
OUTP
XN
OUTN
DP
DN
CKP
XP
CKN
XN
CKN
CKP
CKP/N
Output OUTP/N is synchronized with
CKP/N falling edge.
DP/N
OUTP/N
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
40
CML Latch Design Considerations
IGG
R
R
slope=1/rgg
VGG
1
ISS
2
dc operating points
VGG
Necessary criterion for bistability:
IGG
rgg =
2
2R
=
<0
1/ R - gm 1- gm R
at middle operating point
(Equivalent to loop gain = gmR > 1)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
41
Avoiding Latch Transparency
gm R > 1
XP/N
gm R » 1
gm R £ 1
“transparent” latch
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
42
QIN
XN
DP
XP
QIP
OUTP
OUTN
DN
CKP
XP
QIP
CKN
QIN
XN
CKN
CKP
GBW parameter
can be increased to
ensure bistability.
R=1000
gmR > 1
R=800
gmR » 1
R=600
gmR < 1
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
43
Buffering Clock Signals (1)
Clock signals (generated from VCO or clock divider) often drive large capacitive loads.
1x
C
…
1x
n
1x
C
C
Fanout = n
For a large fanout, attenuation of clock amplitude will occur.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
44
Buffering Clock Signals (2)
ktp
1x
nx
kx
k2
x
…
m stages
Now
is increased by k << n
less attenuation at each stage
Delay = mktp
Power = P1(1 + k + k2 + … + n)
Power dissipated by first stage
As fclock  1/tp then k  1; number of stages and total power become very large.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
45
Buffering Clock Signals (3)
Since clock signal is made up of a single frequency (+ harmonics),
resonance can be used to increase gain with greatly reduced power dissipation.
1
1
(1- w 2LC) + jw(L / R)
Y = + jwC +
=
R
jwL
jwL
Resonant frequency: wr =
1
LC
Y=
1
at resonance
R
If lossless inductors were available, we could achieve high gain at any frequency
simply by choosing the correct inductor value.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
46
On-Chip Passive Elements
l
R=
Resistor:
t
w
r l
×
t w
l
Capacitor:
C » l ×w ×
w
e
d
(+ fringing)
d
substrate
l
Inductor:
L
t
w
l
é æ 2l ö
t +wù
» 0.2êlnç
ú pH/ m
÷ + 0.50049 +
t
+
w
3
l û
ø
ë è
Inductance calculation much more complicated!
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
47
l
t
L
l
é æ 2l ö
t +wù
» 0.2êlnç
ú pH/ m
÷ + 0.50049 +
t
+
w
3
l
ø
ë è
û
w
Special case of Greenhouse result
Note for l >> w, L is a weak function of w
To increase effective inductance per unit length, we make use of
mutual inductance via spiral structure:
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
48
Modeling of Spiral Inductor
1
2
Accurate lumped model should include:
• Series inductance (self + mutual) & resistance
• Skin effect (frequency dependent series resistance)
• Interwinding capacitance
• Capacitance to substrate
• Substrate capacitance & loss
number of turns n = 2
Design of inductor requires:
• inductor simulation package
(e.g., asitic)
• trial and error
• conversion to lumped
element model
EECS 270C / Winter 2014
Procedure for constructing lumped model:
1. 2-port s-parameters over frequency range of interest
(this comes from the inductor simulator)
2. Choose lumped circuit topology.
3. Run simulations to find the optimal lumped circuit
element values such that the the circuit s-parameters
are sufficiently close to the inductor’s s-parameters
(can use .net and .optimize in HSPICE)
Prof. M. Green / U.C. Irvine
49
Modeling of Spiral Inductor (cont.)
Link to “asitic” web pages:
http://rfic.eecs.berkeley.edu/~niknejad/asitic.html
Inductor magnitude impedance vs. frequency
Parameters most relevant to circuit designers:
• Inductance
• Series resistance
• Self-resonant frequency
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
50
Modeling of Spiral Inductor (cont.)
Cint
1
1
2
L
Cox1
2
Rsub1 Csub1
L:
Rs :
Cint:
Cox:
Csub/Rsub:
Rs
Cox2
Csub2 Rsub2
Self/mutual inductance
Series resistance
Interwinding capacitance
Oxide capacitance
Substrate capacitance/resistance
Values of L and Rs in lumped model should correlate with physical parameters.
Values of other lumped model elements need not necessarily correlate with physical parameters.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
51
Parasitic capacitances usually combine with load capacitance  L should be decreased slightly
Series Rs has more important effect:
L
C
L'
R
C
R’
Rs
Y=
1
1
+ jwC +
R
Rs + jwL
Y¢ =
1
1
+ jwC +
R¢
jwL¢
At resonance, Im [Y(j r)] = 0:
2
1 æ Rs ö
wr =
-ç ÷
LC è L ø
2
wr =
2
( )
Y ¢ jwr =
1 CRs
Y jwr = +
R
L
( )
L
L¢ =
1-
2
CRs
L
1
R¢
æ L ö
R¢ = R || ç
÷
è CRs ø
Slight increase in effective inductance
EECS 270C / Winter 2014
1
L¢C
Very important effect!
Prof. M. Green / U.C. Irvine
52
CML Tuned Amplifiers (1)
Differential-mode ground
Sets common-mode
output voltage
CL resonates out with L
Gain at resonant frequency = gm R’
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
53
CML Tuned Amplifiers (2)
Symmetric inductor structure can be used:
Single structure allows more inductance to
be realized from mutual coupling
 less series resistance
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
54
CML Tuned Amplifiers (3)
Higher-gain topology:
Gain is much higher at resonance, but depends completely on Rs.
Variation in gain correlates with variation in metal (not resistor) sheet resistance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
55
CML Tuned Amplifiers (4)
Watch out for ac current amplitude in inductors!
Iin
+
IL
Vswing
L’
C
R’
_
Iin =
Vswing
R¢
IL =
Vswing
wL¢
Let Vswing = 500mV, L=0.5nH, f =10GHz:
IL = 16mA
Spiral inductor should be wide enough
to meet ac electromigration specs.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
56
Inductors in Broadband Circuits
LC lossless
transmission line
(Z0)
R
+
R
Vin
1
H(s) = ×
2
| H( jw) |
1
CR
1+ s
2
0.5
ÐH( jw)
Vout
_
1 -sTd
×e
2
for R = Z0
Td = LC
H(s) =
| H( jw) |
0.5
2
CR

ÐH( jw)



slope = -Td
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
57
Series Peaking (1)
With direct connection of 2 buffers,
output & input capacitances are in parallel:
Cd
Cg
By connecting an inductor between the
capacitors, the bandwidth and delay increase:
Lser
Cd
Cg
“Series peaking”
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
58
Series Peaking (2)
R
Using R »
Vx-
Vin+
Vin-
Lser
Cd
Vx+
Lser
Cd
set Lser » Cd R2
Series peaking provides speed at the
expense of extra delay.
Cg
Cd = Cg = 16 fF
R = 400 
Frequency response:
Vx
Vin
Lser = 0
BW = 6.3 GHz
Transient response:
Vx (Lser = 3.5 nH)
Lser = 3.5 nH
BW = 8.3 GHz
æV ö
Ðç x ÷
è Vin ø
Vx (Lser = 0)
Vin
Lser = 3.5 nH
Lser = 0
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
59
Shunt-Peaking (1)
By connecting an inductor in series with the load
resistor (series connection in shunt with output),
more current is used, for a longer time, to charge
the load capacitance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
60
Properties of Shunt-Peaking
Frequency response:
CL
L
R
Z(s) = R ×
1+ sCL R + s 2LCL
L
R
Z( jw ) = R ×
2
1- w LCL + jwCL R
1+ jw
(
)
1+ s
Resonant frequency:
1 æ CL R2 ö
wr =
ç1÷
LCL è
L ø
2
Im s
X
OX
Re s
L
<1
No resonance for
2
CL R
L = 0:
L ≠ 0:
zero at s = −R/L pole at s = −1/RC
additional pole at
s ≈ −(1/CR + R/L)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
61
Shunt-Peaking -- AC Response
L
= 0.3
CL R2
L = 1.8 nH
BW = 9.4 GHz
L=0
Use of shunt-peaking
increases small-signal bandwidth
EECS 270C / Winter 2014
BW = 6.3 GHz
Prof. M. Green / U.C. Irvine
L
= 0.6
CL R2
L = 3.7 nH
BW = 14.3 GHz
62
Shunt Peaking − Transient Response
Step Response:
Pulse Response (Dtin = 50 ps):
L = 3.7 nH
Dtout = 50.8 ps
ISI = 16 mUI
L = 3.7 nH
td = 6.7 ps
L = 1.8 nH
td = 8.5 ps
L=0
L = 1.8 nH
Dtout = 50.0 ps
ISI = 0 mUI
L=0
Dtout = 48.7 ps
ISI = 26 mUI
td = 13.4 ps
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
63
Shunt Peaking – ISI vs. Pulse Width
ISI (UI)
L
= 0.6
2
CL R
L
=0
2
CL R
L
= 0.3
2
CL R
Input pulse width
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
64
Other Advantages of Shunt-Peaking
• CML load is passive & linear
• Can be shown to be very robust in the presence of parasitic
series resistance and shunt capacitance  inductors can be
placed far away from other CML circuit elements.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
65
Effect of Shunt-Peaking Inductor Parasitics (1)
L
L
L
CP
CP
L
long metal lines
RP
R
R
CL
CL
RP
R
R
CL
CL
• Series resistance RP simply adds to R
• Shunt capacitance CP resonates with L …
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
66
Effect of Shunt-Peaking Inductor Parasitics (2)
ISI (UI)
L
= 0.6
CL R2
CP = 0
L
=0
CL R2
Moderate amount of parasitic capacitance
has similar effect to slightly larger inductor.
L
= 0.3
CL R2
Input pulse width
ISI (UI)
L
= 0.6
CL R2
CP = 0.2CL
Disadvantages of using passive inductors:
• Consume huge die area
• Difficult to design & model
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
L
=0
CL R2
L
= 0.3
CL R2
Input pulse width
67
Multi-layer Inductors (1)
metal 6
metal 6
d
metal 5
metal 5
d
Distance d between two metal layers is much smaller than lateral distances
(e.g., w, l, s)
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
68
Multi-layer Inductors (2)
2-port representation of coupled inductors:
M = k L1L2
i1
i1
i2
+
1
series connection of coupled inductors:
L1
L2
_
M
+
+
1 L1
2
L2 2
_
_
_
+
Passivity constraint: k £ 1
i2
fseries = f1 + f2 = (L1 + M)i 1 + (L2 + M)i 2
æf ö é L M ùæ i ö
1
ç 1÷=ê 1
úç ÷
èf 2 ø ëM L2 ûèi 2 ø
i series = i 1 = i 2
For metal geometries close to each other,
k is close to unity.
Þ
Lseries =
fseries
i series
= L1 + L2 + 2M
For L1 = L2 = L, we have: Lseries = 2L + 2M = 2L(1+ k) » 4L
2
In general, for n layers we have: Lseries » n L
Multi-layer inductors are more appropriate for shunt-peaking than resonant structures
due to additional contact resistance.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
69
Multi-layer Inductors (3)
Effective Capacitance:
Leffective » 4L
1
1
Ceffective » Ci + C j
3
12
Ci
Cj
For more details, see:
A. Zolfaghari, A. Chan & B. Razavi, “Stacked inductors and transformers in
CMOS technology,”
IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp. 620-628.
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
70
Multi-layer Inductors (4)
Area comparison:
metal 6 only
100 x 100
w = 4; s = 2; n = 4
L=2.0 nH
R=6.9 
metal 6 over metal 4
46 x 46
w = 4; s = 2; n = 2.5
L=2.0 nH
R=12.5 
+
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
71
Active Inductors (1)
Impedance inversion:
Ideal gyrator:
i1
Rgyr
i2
iin
+
+
+
v1
v2
vin
_
_
_
v 2 = Rgyr i1
( )
Matrix representation (Z-parameters):
EECS 270C / Winter 2014
-Rgyr ùæ i1 ö
úç ÷
0 ûèi 2 ø
C
2
Zin = Rgyr
sC
v1 = -Rgyr i 2
æv ö é 0
ç 1÷ = ê
èv 2 ø ëRgyr
Rgyr
Port 1 exhibits inductance when
port 2 is connected to a capacitance.
Prof. M. Green / U.C. Irvine
72
Active Inductors (2)
Consider common-drain configuration:
i1 applied with port 2 open-circuited:
v2 =
i2
RG
1
i1
gm
i2 applied with port 1 open-circuited:
+
v2
_
_
v1
i1
æ
1ö
v1 = -çRG - ÷i 2
gm ø
è
(Assume RG gm > 1)
+
Complete Z-parameters (lossy/active gyrator):
(
æ v ö é1 g - R -1 g
G
m
ç 1÷ = ê m
1 gm
èv 2 ø êë1 gm
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
)ùúæç i ö÷
1
úûèi 2 ø
73
Active Inductors (3)
Interpretation of non-ideal matrix entries:
+
æ v ö é1 g 1 g - R ùæ i ö
m
G
1
ç 1÷ = ê m
úç ÷
1 gm ûèi 2 ø
èv 2 ø ë1 gm
vin
_
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
74
Active Inductors (4)
Impedance at port 1 with port 2 terminated with transistor Cgs:
At low frequencies (Cgs open)  Zsource = 1/gm
At high frequencies (Cgs short)  Zsource = RG
Zsource
EECS 270C / Winter 2014
1 é 1+ sCgs RG ù
=
ê
ú
gm ë1+ s Cgs gm û
Prof. M. Green / U.C. Irvine
75
Active Inductors (5)
Equivalent circuit:
Zsource
Leff »
Cgs RG
gm
=
RG
wT
RG
1
gm
+
vin
1
gm
1
Cgs RG
gm
Cgs
w
Cgs ×
_
RG
gm
RG -
1
gm
gmRG > 1
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
76
CML Buffer with Active Inductor Load
Low-frequency gain:
Av =
gm 1
W1
=
gm 2
W2
For shunt peaking:
L » 0.3CL R2
Cgs RG
gm 2
æW ö
4
ç ÷ =
è L ø1 0.18
= 0.3
æW ö
2.5
ç ÷ =
è L ø2 0.18
CL
gm2 2
gm 2RG = 0.3
CL
Cgs
ISS = 400 mA
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
77
Active Inductor AC Response
RG = 4k
RG = 2k
RG = 0
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
78
Active Inductor Transient Response (1)
Differential signals:
RG = 0
PW = 97ps
RG = 5k
PW = 100 ps
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
RG = 10k
PW = 104 ps
79
Active Inductor Transient Response (2)
Single-ended signals:
Problem: n-channel load shifts output by Vt.
Vsb > 0; body effects exacerbates this effect..
Single-ended
input
Single-ended
outputs
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
80
Active Inductor Alternate Topology
Alternate topology:
p-channel load exhibits lower Vt
(Vbs = 0)
differential
single-ended
EECS 270C / Winter 2014
Prof. M. Green / U.C. Irvine
81