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CE01000-3 Operating Systems
Lecture 2
Low level hardware support for
operating systems
Announcement
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Next week – I am not available to teach on
Monday, so the Monday lecture will be
rescheduled to Tuesday at 5pm in Green LT
Just for next week
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Lectures – Tuesday 10am Green LT
Tuesday 5pm Green LT
Overview of lecture
In this lecture we will be looking at low level
hardware facilities that are needed to support
operating systems
 In particular we will look at:
1. How computer system operation requires
interrupts and how interrupts are handled
2. How CPU dual mode operation can control
which programs can execute which
instructions
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3. The need to provide mechanisms to protect
the CPU, memory and I/O from being used to
corrupt the proper operation of the system
4. Direct Memory Access & the memory
hierarchy
Computer-System operation is
interrupt driven
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I/O devices and the CPU can execute
concurrently.
So we need a mechanism for the running
program to begin I/O and for I/O devices to
signal that it has completed whatever I/O has
been requested
Each type of I/O device has a piece of
hardware called a device controller which
controls the operation of the I/O devices.
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Each device controller has a local buffer.
CPU moves data from main memory to the
local buffer and vice versa.
Actual I/O occurs between the device and the
local buffer of controller.
Device controller informs CPU that it has
finished its operation by causing an interrupt.
Operating system is interrupt
driven
These are the
devices that make
up a typical system.
Any of these
devices can cause
an electrical
interrupt that grabs
the attention of the
CPU.
I/O processing
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High level view of I/O interrupt processing
Interrupt Handling
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An interrupt is a signal that stops execution
of currently executing program because some
other code needs to use the CPU to deal with
the request for service
This interrupt may be from
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I/O device – signaling I/O completion
Hardware signaling some fault/error or problem
that needs dealing with e.g. power low on a
laptop
Running program itself (software interrupt) –
will be discussed more later
Interrupt Handling (Cont.)
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The operating system saves the state of the
CPU by saving various working registers and
the program counter.
The OS then determines which type of
interrupt has occurred by either:
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Polling
Using vectored interrupts
Interrupt Handling (Cont.)
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Polling involves checking device controller
status registers to see if device needs service
and if service required invoking appropriate
code
Vectored interrupt system - uses a table of
addresses (called vectors) of interrupt service
routines (ISRs) - interrupt passes to OS a
number which is an index into the table - thus
identifies which ISR needs to be executed
Interrupt Handling (Cont.)
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Interrupt Service Routine (ISR) - part of
OS - carries out appropriate action for each
type of interrupt
when ISR has finished the OS either
restores the state of CPU (restores saved
register values of program that was
interrupted into correct registers in CPU) or
invokes scheduler to determine whether a
different program should run next
Interrupt Handling (Cont.)
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Incoming interrupts are disabled while another
interrupt is being processed to prevent a lost
interrupt
However, you can organise interrupts into
priority levels, so that interrupts of a higher
priority can interrupt interrupts of a lower
priority level
Interrupt Handling (Cont.)
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A trap is a software-generated interrupt
caused either by a software error (e.g. attempt
to divide by zero) or an instruction executed
as part of the running program – it is the
means by which the running program can
signal the operating system that it needs the
operating system to do something for it - how
system calls (see later) are ultimately
implemented
CPU Dual-Mode Operation
- the need for it
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Why does user program need to ask OS to do
things for it?
User programs do not run in isolation but run on
system with other programs
System resources need to be shared between
these programs and this requires operating
system to ensure that one program cannot cause
other programs to execute incorrectly.
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Programs must not interfere with each other
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Thus a normal user program must not be
allowed to use instructions that could corrupt
the proper execution of other programs.
CPU Dual-Mode Operation
- what it is
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To prevent user programs from executing
instructions that might corrupt another user’s
programs dual-mode operation was introduced.
CPU needs at least 2 modes of operation:
1. User mode – when executing user programs CPU only permits execution of subset of its
instruction set.
2. Supervisor mode (also called monitor or system
mode) – when executing operating system - can
execute all instructions.
CPU Dual-Mode - how it works
CPU Dual-Mode - how it works
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Mode bit added to computer hardware to
indicate the current mode: supervisor (0) or
user (1).
When an interrupt or fault occurs hardware
switches to supervisor mode - when OS
restarts user program it switches it to user
mode
instructions that can only be used in
supervisor mode are called Privileged
instructions.
Only OS runs in supervisor mode
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Must ensure that a user program never gains
control of the computer in supervisor mode
At system start only OS is running - in
supervisor mode
just before running a user program OS switches
CPU to user mode
user program then runs - in user mode
Of course changing mode bit needs to be a
privileged instruction
Only OS runs in supervisor mode
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CPU goes into supervisor mode only when an
interrupt occurs
When interrupt occurs, user program is halted
temporarily and control of CPU is passed to
ISR for the interrupt – but ISR is part of OS
Thus only OS runs in supervisor mode
Dual-mode operation implies need
for memory protection
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BUT what if user program stores the address
of part of its own code in an interrupt vector it can gain control of CPU in supervisor mode.
Thus system memory needs some form of
protection
Memory Protection
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Must provide memory protection for the
interrupt vector and the interrupt service
routines - but also user programs and data
One simple mechanism to provide memory
protection - add two registers that determine
the range of legal addresses a program may
access:
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base register – holds the smallest legal
physical memory address.
limit register – contains the size of the range.
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Attempt to access memory outside range
causes an error interrupt to OS to deal with
problem
Example Memory Protection
Memory protection using
base/limit registers
Memory protection using
base/limit registers
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When executing in supervisor mode, the
operating system has unrestricted access to all
of memory – memory of OS itself and each
users’ memory.
The load instructions for the base and limit
registers need to be privileged instructions.
CPU Protection
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What if a user program goes into an infinite
loop?
We need something that will enable OS to
gain control of CPU so it can stop running
program and start other programs.
Timer – interrupts computer after specified
time has elapsed to ensure operating system
can maintain control.
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Timer is decremented every clock tick.
When timer reaches 0, an interrupt occurs.
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Timer commonly used to implement time
sharing.
Timer also used to compute the current time.
Loading the timer needs to be a privileged
instruction.
I/O structure
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a) synchronous I/O
b) asynchronous I/O
I/O Structure
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Synchronous I/O - after I/O starts, control
returns to user program only when I/O
completed.
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CPU waits by executing an instruction that
makes it go idle until next interrupt or goes into a
busy loop repeatedly polling device to see if I/O
completed.
at most one I/O request is outstanding at a time;
no simultaneous I/O processing.
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Asynchronous I/O - after I/O starts, control
returns to user program without waiting for
I/O to complete.
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This needs a device-status table to contain entries
for each I/O device indicating its type, address,
and state
Multiple requests for particular I/O can then be
queued (linked list) on the device
OS indexes into device table to determine device
status
Device status table
I/O Protection
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To prevent one user program from
interfering with the output or input of data
that belongs to another user program all I/O
instructions are privileged instructions.
System calls
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Given that I/O instructions are privileged,
how does the user program perform I/O?
System call – this is the method used by a
running program to request action by the
operating system.
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Usually takes the form of a trap (software
interrupt) – we met these earlier
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The trap (software interrupt) will provide an
interrupt vector to identify the interrupt service
routine (ISR) required, the mode bit will then be
set to supervisor mode and ISR begins execution.
The running program passes information to OS
about the exact service it requires via parameters
to system call
OS verifies that this information (parameters) are
correct and legal, executes the request, and returns
control to the instruction following the system
call.
System call sequence
Direct Memory Access (DMA)
Direct Memory Access (DMA)
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Direct Memory Access is used for high-speed
I/O devices able to transmit information at
close to memory speeds.
Device controller transfers blocks of data from
buffer storage directly to main memory
without CPU intervention - uses cycle
stealing
Only one interrupt is generated per block of
data, rather than the one interrupt per byte.
Memory Structure
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Main memory – only large data area that the
CPU can access directly - but
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volatile
not large enough to hold all data/programs
Secondary memory – extension of main
memory that provides large nonvolatile
storage capacity
Memory Hierarchy
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Storage systems organized in hierarchy:
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higher levels give more speed, but at greater cost
and with greater volatility
Storage-Device Hierarchy
Caching principle
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Caching principle – maintaining a copy of
some of the information from a slower storage
medium on a faster medium; information held
in cache is that currently being used.
main memory can be viewed as a fast cache
for secondary memory
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problem - to provide mapping between copy and
original information and maintain consistency
between them both
References
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Operating System Concepts. Chapter 1.