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970
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 11, NOVEMBER 1997
specifications—N odd, K = 0:2; fp = 0:43; fs = 0:57 and s <
0.01 (040 dB). This filter has (fp + fs )=2 = 0:5: Substituting
K = 1=0:2 into (13) and s = 0:01 2 0:2 into (8) gives the
estimated value of N as 23.6. The linear programming results of s
for filters with N = 23 and N = 25 are 038.0 dB and 041.2 dB,
respectively. The selected value of N should be 25.
IX. CONCLUSION
This paper investigates some of the properties of the linear phase
diamond-shaped 2-D FIR low-pass filters. A set of design rules
applicable to the design of such filters optimal in the minimax error
sense is presented. Over 1000 low-pass diamond-shaped filters were
designed using linear programming to form the data base used to
formulate the set of design rules. The design rules provide good
estimates for the minimum filter support size required to meet a given
specification set. From our experience, the maximum relative error
in the estimated filter support size is 10%; in most cases, it is less
than 5%.
ECL Storage Elements: Modeling of Faulty Behavior
Sankaran M. Menon, Yashwant K. Malaiya,
and Anura P. Jayasumana
Abstract— Bipolar emitter coupled logic (ECL) devices can now be
fabricated at very high densities and much lower power consumption.
Behavior of two different ECL storage element implementations are
examined in the presence of physical faults. While fault models for some
implementations of CMOS storage elements have been examined, not
much attention has been paid to ECL storage elements. The conventional stuck-at fault model termed minimal fault model assumes that an
input(output) of a storage element can be stuck-at-1 or 0. The minimal
fault model may not model the behavior under certain physical failures in
a storage element. The enhanced fault model providing higher coverage
of physical failures is presented.
Index Terms—Emitter coupled logic, fault modeling, faulty behavior,
storage elements.
I. INTRODUCTION
REFERENCES
[1] O. Herrmann, L. R. Rabiner, and D. S. K. Chan, “Practical design rules
for optimum finite impulse response low-pass digital filters,” Bell Syst.
Tech. J., vol. 52, no. 6, pp. 769–799, July–Aug. 1973.
[2] L. R. Rabiner and B. Gold, Theory and Application of Digital Signal
Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975.
[3] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing. Englewood Cliffs, NJ: Prentice-Hall, 1975, ch. 5.
[4] F. Mintzer and B. Liu, “Practical design rules for optimum FIR bandpass
digital filters,” IEEE Trans. Acoust., Speech, Signal Processing, vol.
ASSP–27, pp. 204–206, Apr. 1979.
[5] P. Siohan, “2-D FIR filter design for sampling structure conversion,”
IEEE Trans. Circuits Syst. Video Technol., vol. 1, pp. 337–350, Dec.
1991.
[6] S.-C. Pei and J.-J. Shyu, “Design of two-dimensional FIR eigenfilters
for sampling-structure conversion,” IEEE Trans. Circuits Syst. Video
Technol., vol. 3, pp. 158–162, Apr. 1993.
[7] Günter Schamel, “Pre- and postfiltering of HDTV signals for sampling
rate reduction and display up-conversion,” IEEE Trans. Circuits Syst.,
vol. CAS–34, pp. 1432–1439, Nov. 1987.
[8] R. M. Mersereau and T. C. Speake, “The processing of periodically
sampled multidimensional signals,” IEEE Trans. Acoust., Speech, Signal
Process., vol. ASSP–31, pp. 188–194, Feb. 1983.
[9] E. Dubois, “The sampling and reconstruction of time-varying imagery
with applications in video systems,” Proc. IEEE, vol. 73, pp. 502–522,
Apr. 1985.
[10] R. Manduchi, G. M. Cortelazzo, and G. A. Mian, “Multistage sampling
structure conversion of video signals,” IEEE Trans. Circuits Syst. Video
Technol., vol. 3, pp. 325–340, Oct. 1993.
[11] P. Carrai, G. M. Cortelazzo, and G. A. Mian, “Characteristics of
minimax FIR filters for video interpolation/decimation,” IEEE Trans.
Circuits Syst. Video Technol., vol. 4, pp. 453–467, Oct. 1994.
[12] Y. C. Lim, “Efficient special purpose linear programming for FIR filter
design,” IEEE Trans. Acoust., Speech, Signal Processing, vol. ASSP–31,
pp. 963–968, Aug. 1983.
[13] R. H. Yang and Y. C. Lim, “Grid density for design of one- and twodimensional FIR filters,” Electron. Lett., vol. 27, no. 22, pp. 2053–2055,
Oct. 1991.
[14] V. Ouvrard and P. Siohan, “Design of two-dimensional video filters
with spatial constraints,” in Proc. EUSIPCO-92, Aug. 1992.
[15] D. W. Marquardt, “An algorithm for least squares estimation of nonlinear parameters,” J. Soc. Ind. Appl. Math., vol. 2, pp. 431–441, 1964.
[16] J. G. Reich, C Curve Fitting and Modeling for Scientists and Engineers.
New York: McGraw-Hill, 1992.
Emitter coupled logic (ECL) using bipolar technology is generally
used in applications where switching speed is more important than
power dissipation and cost. Conventional bipolar ECL technology
represents the state of the art in silicon speed, providing system
propagation delays in the subnanosecond range but the price paid
for such speeds is very high power dissipation (1.5 mW or more
per gate—way too much for VLSI densities) [1]. Recent advances
in technology such as BIT1 [1] developed by Bipolar Integrated
Technology have made it possible to fabricate bipolar ECL devices
that take about 1/20 th the area of conventional ECL devices with
speeds comparable to the fastest ECL, consuming only one-tenth the
power [1].
With the achievement of low power, high speed, as well as high
density, ECL technology is expected to be used widely in various high
performance digital circuits [2]. Even more highly integrated bipolar
and bipolar/MOS chips are expected in future, further narrowing the
gap between low cost workstations and high performance servers [2].
Transistor level shorts and opens model many of the physical
failures and defects in IC’s [3]. Analysis of faults in simple logic
circuits suggest that transistor level testing provides a higher coverage
of faults compared to that at gate level [4]. It is necessary to study
the effects of failures at the transistor level and develop accurate fault
models at this level [3]. The major fault models at transistor level are
stuck-at faults, stuck-shorts and opens of transistor and interconnects,
and bridging faults [5].
The issue of fault modeling of 1- and 2-level ECL gates have
been addressed in [6] and [7], where augmented fault models were
presented which provide higher coverage of physical failures. Effects
of bridging faults in ECL circuits was presented in [8] and [9].
Since testing of sequential circuits is difficult, one of the common
approaches is to convert the problem into simpler problem of testing
Manuscript received October 1, 1994; revised July 3, 1995. This work was
supported by a BMDO funded project monitored by ONR. This paper was
recommended by Associate Editor M. Soma.
S. M. Menon was with the Department of Electrical and Computer
Engineering, South Dakota School of Mines and Technology, Rapid City,
SD 57701 USA. He is now with Texas Instruments, Dallas, TX 75266 USA.
Y. K. Malaiya and A. P. Jayasumana are with the Departments of Computer
Science and Electrical Engineering, Colorado State University, Fort Collins,
CO 80523 USA.
Publisher Item Identifier S 1057-7130(97)07650-7.
1057–7130/97$10.00  1997 IEEE
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 11, NOVEMBER 1997
Fig. 1. ECL storage element-1.
combinational circuits. Design for testability approaches are used to
provide direct access to inputs and outputs of combinational blocks
[4], [10]. Assuming that most faults within a storage element can
be modeled as stuck-at-0/1 faults on the outputs, then the same
faults need not be explicitly considered. This is because such faults
are equivalent to the stuck-at faults in the combinational logic
surrounding the storage elements.
While much work has been done examining physical failures in
CMOS latch cells [11]–[14], not much attention has been paid to ECL
storage elements. ECL storage elements are used in designs involving
high speed communications and networking. Inadequacy of minimal
fault model in representing physical failures for CMOS storage
elements is presented in [15], and enhanced fault model is presented
providing a higher explicit coverage than the minimal fault model.
In this brief, we first examine the behavior of two different ECL
storage elements under various physical failures. Minimal enhanced
fault models are applied to check for its adequacy. It is observed that
the minimal fault model does not provide sufficient coverage. The
enhanced fault model provides higher coverage of physical failures.
The brief is organized as follows. Sections II and III deal with
two different implementations of ECL storage elements and stuckat model, respectively, for ECL storage elements. Section IV deals
with analysis of physical failures in ECL storage elements. Finally
conclusions are given in Section V.
II. ECL STORAGE ELEMENTS
The ECL logic levels recognized by the storage elements for logic
level low are between 01.85 and 01.45 V and for logic level high
are between 01.15 and 00.75 V. The intermediate level between
01.45 and 01.15 V is termed “Indeterminate” logic level. Though
the input low logic level (VIL ) is between 01.85 and 01.45 V, an
input between 05.2 and 01.45 V is valid as logic “0.” Similarly,
though the input high logic level (VIH ) is between 01.15 and 00.75
V, an input between 01.15 and 0.00 V is also logic “1.” These voltage
levels could occur under some faults in ECL storage elements. Such
a situation does not occur in CMOS devices as the output voltage
levels reach the extreme voltage levels of 0 and 5 V for logic “0”
and “1,” respectively, unlike in ECL devices.
An ECL storage element [16] is shown in Fig. 1. Vref1 and Vref2
form the reference voltages for the differential amplifiers. Vref3 along
with the transistors Q9 and Q10 and resistors R2 and R3 form
971
Fig. 2. ECL storage element-2.
the current sinks. When the clock input is high, the logic level at
input D is clocked into the storage element. The clocked input value
is maintained by the feedback provided by transistor Q7 : Another
storage element [16] is shown in Fig. 2, based on differential amplifier
with bilateral drive. In this scheme, true and complementary outputs
are directly available.
III. STUCK-AT MODEL FOR STORAGE ELEMENTS
Most approaches for modeling of faults rely on the assumption that
the faults in storage elements can be modeled as stuck-at faults at its
inputs and outputs. In many situations, when faults are considered
in the combinational logic, it is implicitly assumed that any internal
faults in a storage element can either be shown to be equivalent to
a stuck-at-output or stuck-at-input, which in turn would appear as
a stuck-at-output of the combinational logic surrounding the storage
element. This is termed a minimal fault model. Stuck-at-0/1 fault at
the input(output) of a storage element is equivalent to the stuck-at-0/1
fault of the combinational logic output feeding (input being fed) by
the storage element. Most Design for Testability (DFT) approaches
rely on the assumption that the faults in storage elements can be
modeled as stuck-at faults at its inputs and outputs. For example,
in LSSD implementations, stuck-at faults at the outputs of latches
are considered as stuck-at faults at the inputs of the combinational
circuit driven by the storage elements. Similarly, stuck-at faults at
the inputs of latches are considered as stuck-at faults at the outputs
of the combinational circuit driving the storage elements. In addition,
the DFT schemes rely on large number of complex storage elements.
We examine the effectiveness of the minimal fault model in
representing physical failures. The results reveal the need for a
more accurate fault model to better represent the physical failures
at transistor level. The results inferred from elementary fault model
can then be used to obtain fault models for complex storage elements.
Improved fault models representing physical failures accurately can
help reduce test generation and fault simulation efforts significantly.
IV. PHYSICAL FAULTS IN ECL STORAGE ELEMENTS
In this section, we evaluate the response of two different ECL
storage elements for various faults. Both the storage elements are
examined for all possible hard failures. Possible hard failures considered include all possible opens and shorts of resistors, transistor
junction opens and shorts. Fig. 3 shows the naming convention used
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 11, NOVEMBER 1997
TABLE I
BEHAVIOR OF ECL STORAGE ELEMENT-1 UNDER OPENS AND SHORTS
(a)
(b)
Fig. 3. Naming convention used for transistors (a) shorts and (b) opens.
for (a) shorts and (b) opens between various junctions of the bipolar
transistor. For simulating shorts between various junctions of the
bipolar transistors, a low resistance of 1 was connected between
the terminals and for opens, a resistance of 10 M
was connected
between the respective terminals. A good functional fault model
which adequately describes the functional behavior of faulty storage
elements is sought. The minimal fault model as well as enhanced fault
models are examined for their effectiveness in representing the faults.
The enhanced fault model proposed in [15], was shown to provide a
higher explicit fault coverage for CMOS storage elements. Data feedthrough faults, which are remarkably different from stuck-at-0/1 faults
were proposed. Such faults cause the storage element to become either
Data or Data-feed-through, which could lead to timing problem
or coupling between combinational blocks separated by the storage
elements [17]. In the two different ECL storage elements examined
in this brief, Data and Data feed-through faults have been observed
and are defined [15] as follows.
Definition 1: A faulty storage element is said to have a feedthrough fault if it becomes Data feed-through or Data feed-through.
1) A faulty storage cell is said to be Data-feed-through when its
behavior becomes combinational such that R(s; ti ) = f (y ) for
each ti 2 T ; where y is the data part of ti :
The above definition is modified to include data feed-through
faults, which is defined as shown in Definition 2.
Definition 2: A faulty storage element is said to have a feedthrough fault if it becomes data-feed-through.
1) A faulty storage cell is said to be data-feed-through when its
behavior becomes combinational such that R(s; ti ) = f (y )
for each ti 2 T ; where y is the data part of ti : where
T = ft1 ; 1 1 1 ; tn g are the set of all possible input combinations.
For an elementary synchronous storage element with input D
and a control signal C LK; and n = 4. R(s; ti ) is the response
of the cell to the input vector ti applied to the cell when the
cell is at state s:
To avoid glitches and hazards in clocked storage elements, clock
is applied when the data is stable. The latch is race-free if the data
is stable when clock is active [11]. Hence, data (D) is allowed to
change only when clock (C LK ) is low. Certain faults cause change
in behavior of the synchronous storage element in latch phase, while
functioning properly in the transparent phase. This causes the cell to
be unable-to-latch 1(0) and is defined [15] below.
Definition 3: Let the state of a faulty synchronous elementary
storage element during the transition from the transparent phase to
the latch phase be Q = 1(0). If the state of the cell becomes 0(1)
during the latch phase irrespective of data input, then the cell is said
to be unable-to-latch 1(0). The notation U L 0 1(U L 0 0) is used
to describe this.
The ECL storage element-1 was analyzed for all input vectors
under shorts and opens between the junctions of all transistors. The
outputs were verified by performing SPICE [18] simulations and the
results are tabulated in Table I. While some faults do not cause any
appreciable change in the logic level exhibiting fault-free level, some
faults manifest as stuck-at-1 or stuck-at-0. Six faults cause the cell
op
=
=
=
Open, sh
Short, (e, b, c emitter,
base, collector), @ Abnormal Current.
=
to be transparent with Q output being the same as D and therefore
the cell exhibits Data-feed-through. For one of the faults, the output
becomes a logical function of the clock signal and is termed as
complex behavior. Behavior exhibiting unable to latch-1 and unable
to latch-0 are observed for 2 and 9 faults, respectively.
Out of the 68 faults considered, 46 faults (67.6%), are covered
by the minimal fault model, while the enhanced fault model covers
17 more resulting in 63 faults (92.6%). Three faults manifesting as
indeterminate output and 2 faults exhibiting complex behavior cannot
be modeled either by minimal fault model or by the enhanced fault
model.
Results obtained for ECL storage element-2 Q output is summarized in Table II. Twenty faults do not cause any appreciable change
in the logic level at Q output exhibiting fault-free output. Some faults
manifest as stuck-at-1 or stuck-at-0. Five faults cause the cell to
exhibit data feed-through. For four of the faults, the output becomes
a logical function of the clock signal and is termed as complex
behavior. Behavior exhibiting unable to latch-1 and unable to latch0 are observed for five and 11 faults, respectively. Out of the 90
faults considered, 53 faults (58.8%), are covered by the minimal fault
model, while the enhanced fault model covers 21 more resulting in 74
faults (82.2%). Twelve faults manifesting as indeterminate output and
three faults exhibiting complex behavior cannot be modeled either by
minimal fault model or by the enhanced fault model.
Results obtained for ECL storage element-2 Q output is summarized in Table III. Twenty faults do not cause any appreciable
change in the logic level at Q output exhibiting fault-free output.
Some faults manifest as stuck-at-1 or stuck-at-0. Seven faults cause
the cell to exhibit Data feed-through. For two of the faults, the
output becomes a logical function of the clock signal and is termed as
complex behavior. Behavior exhibiting unable to latch-1 and unable
to latch-0 are observed for 5 and 10 faults, respectively. Out of the
90 faults considered, 53 faults (58.8%), are covered by the minimal
fault model, while the enhanced fault model covers 22 more resulting
in 75 faults (83.3%). 13 faults manifesting as indeterminate output
and 2 faults exhibiting complex behavior cannot be modeled either
by minimal fault model or by the enhanced fault model.
Two faults (R2sh and R3sh ) in ECL storage element-1 and four
faults (R3sh ; R4sh ; R5sh and R6sh ) in ECL storage element-2 cause an
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 11, NOVEMBER 1997
TABLE II
Q OUTPUT OF ECL STORAGE ELEMENT-1 UNDER OPENS AND SHORTS
973
times. A current monitor to monitor the power supply current (IEE )
can be used to detect the enhanced current drawn by the device and
work is underway to develop such a scheme.
On careful observation of Tables II and III indicate that for 14 of
the physical failures (15%) marked 3; the input test vectors cause both
the true and complementary outputs to exhibit similar outputs (00 or
11), i.e., exhibits loss of complementarity. Under fault-free conditions,
the Q and Q outputs exhibit fault-free dissimilar outputs (01 or 10).
A simple testable design using an exclusive-OR or an exclusive-NOR
gate can be used to detect the loss of complementarity occurring at the
outputs of ECL storage elements. Use of an exclusive-OR or exclusiveNOR to detect loss of complementarity may be a severe penalty to pay
in terms of area overhead. However, this approach is effective and
a scheme to implement this logic with less number of transistors is
underway.
V. CONCLUSIONS
op = Open, sh = Short, (e, b, c, = emitter, base, collector),
* = Loss of Complementarity, @ = Abnormal Current.
Physical failures in two different ECL storage elements have been
examined. High fault coverage may not be obtained using the minimal
fault model for ECL storage elements. The enhanced fault model
provides higher explicit coverage of physical failures compared to the
minimal fault model. The enhanced fault model includes faults that
cause the cell become Data or Data feed-through as well as faults
that cause the cell unable to latch High or Low signals. When modest
fault coverage is needed, the minimal fault model may be sufficient.
However, in situations where higher fault coverage is sought, the
enhanced fault model may be able to provide higher coverage of
physical failures. Power supply current monitoring can be used for
detection of certain types of faults in ECL storage elements.
TABLE III
Q OUTPUT OF ECL STORAGE ELEMENT-1 UNDER OPENS AND SHORTS
op = Open, sh = Short, (e, b, c = emitter, base, collector),
3 = Loss of Complementarity, @ = Abnormal Current.
increase current drawn by the device. Normal current drawn by the
device is 6 mA but under the above mentioned faults, the current
drawn by the device increases to 1.3A, an increase of about 200
REFERENCES
[1] G. Wilson, “Creating low-power bipolar ECL at VLSI densities,” VLSI
Syst. Design, May 1986, pp. 84–86.
[2] E. W. Brown, A. Agrawal, T. Creary, M. F. Klein, D. Murata, and J.
Petolino, “Implementing sparc in ECL,” IEEE Micro, pp. 10–22, Feb.
1990.
[3] J. A. Abraham and W. K. Fuchs, “Fault and error models for VLSI,”
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[4] Y. K. Malaiya, B. Gupta, Anura P. Jayasumana, R. Rajsuman, S. Menon,
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elements,” in IEEE Comput. Soc. 12th Annual IEEE Workshop Design
for Testabil., Apr. 18–21, 1989.
[5] C. C. Beh, K. H. Arya, C. E. Radke, and K. E. Torku, “Do stuck faults
models reflect manufacturing defects?” in Proc. IEEE Test Conf., Nov.
1982, pp. 35–42.
[6] S. M. Menon, A. P. Jayasumana, and Y. K. Malaiya, “Fault modeling
of ECL devices,” Electron. Lett., pp. 1105–1108, July 1990.
[7] S. M. Menon, Y. K. Malaiya, and A. P. Jayasumana, “Fault modeling
and testable design of 2-level complex ECL gates,” in Proc. 4th
CSI/IEEE Int. Symp. VLSI Design, Jan. 1991, pp. 23–28.
[8] S. M. Menon, Y. K. Malaiya, and A. P. Jayasumana, “On Bridging
Faults in ECL Circuits,” in Proc. 5th CSI/IEEE Int. Symp. VLSI Design,
Jan. 1992, pp. 55–60.
[9] S. M. Menon, A. P. Jayasumana, and Y. K. Malaiya, “Modeling and
analysis of bridging faults in emitter coupled logic (ECL) circuits,” IEE
Proc., Part E: Comput. Digital Tech., vol. 140, no. 4, July 1993, pp.
220–226.
[10] V. D. Agrawal, S. K. Jain, and D. M. Singer, “Automation in design
for testability,” in IEEE 1984 Custom Integrated Circuits Conf., 1984,
pp. 159–163.
[11] M. K. Reddy and S. M. Reddy, “Detecting FET stuck-open faults in
CMOS latches and flipflops,” IEEE Design Test Comput., pp. 17–26,
Oct. 1986.
[12] D. L. Liu and E. J. McCluskey, “A CMOS cell library design for
testability,” VLSI Systems Design, May 4, 1987, pp. 58–65.
[13] R. Anglada and R. Rubio, “Functional fault models for sequential
circuits,” Res. Rep. DEE-3, Elect. Eng. Dept, Polytech. Univ. Catalunya,
Barcelona, Spain, 1987.
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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 44, NO. 11, NOVEMBER 1997
[14] K. J. Lee and M. A. Breuer, “A universal test sequence for CMOS scan
registers,” in IEEE 1990 Custom Integrated Circuits Conf., 1990, pp.
28.5.1–28.5.4.
[15] W. K. Al-Assadi, Y. K. Malaiya, and A. P. Jayasuamana, “Use of storage
elements as primitives for modeling faults in synchronous sequential
circuits,” in 6th Int. Conf. VLSI Design, Jan. 1993, pp. 118–123.
[16] C. Morandi, L. Niccolai, F. Fantini, and S. Gaviraghi, “ECL fault
modeling,” in IEE Proc. Part E, Computers and digital techniques, Nov.
1988, pp. 312–317.
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Fig. 1. Elimination of redundant branches.
Synthesis of High-Speed Pass-Transistor Logic
Vojin G. Oklobdzija and Benoit Duchêne
Abstract—This brief presents new pass-transistor logic which contains
fewer transistors and has better performance than Hitachi’s double passtransistor logic (DPL). The new logic is characterized by excellent speed
and low power.
Index Terms—CMOS, pass-transistor logic.
I. INTRODUCTION
New CMOS logic using pass-transistor circuits has been proposed
recently with the objective of improving speed and power consumption [2]–[4]. The double pass-transistor logic (DPL), developed
by Hitachi demonstrated a 1.5-nS 32-bit ALU and 4.4-nS 54-bit
multiplier in 0.25-m technology [2], [4]. However, DPL has not
yet been fully adopted because of its high transistor count. The logic
proposed here minimizes the number of transistors used in DPL and
preserves the speed. The simulations and tests were performed using
1-m CMOS.
Fig. 2. Signal rearrangement.
II. NEW LOGIC GATE
DVL (dual value logic) gate was obtained by eliminating the
redundant branches and rearrangement of signals in DPL. Signal
rearrangement results in NAND gate configuration which is faster than
DPL (60 pS versus 75 pS), where the AND half is faster. These
simplifications, illustrated in Figs. 1–3, preserve the advantages of
DPL gates.
Finally, we chose a faster half from Fig. 1 and from Fig. 2. The
resulting DVL gate contains total of eight transistors compared to
DPL consisting of four transistors of each type. There is a total of
nine inputs in DVL versus 12 in DPL resulting in a smaller capacitive
load of DVL gate. In DVL, three inputs are connected to the transistor
source and six to the gate (three to p-type and three to n-type). In
Manuscript received June 10, 1995; revised November 12, 1995. This paper
was recommended by Associate Editor S. Kiaei.
V. G. Oklobdzija is with the Advanced Computer System Engineering
Laboratory, Electrical and Computer Engineering Department, University of
California at Davis, Davis, CA 95616 USA.
B. Duchêne is with Ecole Superieure d’Ingenieurs en Electrotechnique et
Electronique, 93162 Noisy le Grand CEDEX, France.
Publisher Item Identifier S 1057-7130(97)07654-4.
Fig. 3. Resulting DVL gate.
TABLE I
COMPARISON BETWEEN DVL
AND
CMOS
DPL 4, inputs are connected to the source and eight to the gate (four
to p-type and four to n-type transistors).
A similar method can be used to build the NOR/OR gates.
Comparison with CMOS: A comparison between DVL and conventional CMOS for given function F2 = BC + ABC is shown in
Fig. 4 and in Table I.
1057–7130/97$10.00  1997 IEEE