Download TECHNICAL QUALIFYING EXAMINATION

MASSACHUSETTS INSTITUTE OF TECHNOLOGY
DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE
TECHNICAL QUALIFYING EXAMINATION
May , 2008
NAME__________________________________________________________
Topic Area: 6.012 – Microelectronic Devices and Circuits
General Instructions:
1.
Please do all of your work in the spaces provided in this examination
booklet. If you need additional sheets, be sure to put your name and the
name of the examination on each sheet.
2.
At the end of the examination, please put this booklet and any extra pages
you have used in the envelope provided
Special Instructions for 6.012
•
•
•
•
Some possible useful formulas and material properties are included on pages 14-20
Where required, make reasonable approximations and state them clearly.
Partial credit will be given for setting up problems without calculations. No credit
will be given fro answers without reasoning.
Every numerical answer should have the proper units next to it. Points will be
subtracted for answers without units or incorrect units.
For examiner’s use only:
Satisfactory
______________
Marginal
______________
Unsatisfactory ______________
1
Problem 1 [40 points]
Diodes D1 and D2 are identical except for their cross sectional areas: A2 = 10 A1. They
are connected in series as shown below.
(a) [5 points] What is the incremental resistance between X and Y?
rXY = _________________
(b) [5 points] What is the difference between the two voltages V1 – V2? [Zero is not
acceptable answer]
V1 – V2 = _____________________________________
2
The n+-p diode (D1) has the following characteristics: A1 = 10 μm x 10 μm, Nd = 1020
cm-3, Na =1017 cm-3, Wn = 0.5 μm, Wp = 1 μm. Use De=20 cm2/s and Dh=5 cm2/s. For
this problem assume that recombination only occurs at the contacts. No recombination in
Space Charge Region (SCR) or Quasi-Neutral Regions (QNR’s).
(c) [5 points] Calculate the value of the saturation current, IS. {Assume xp=0.11 μm}
IS = _______________
3
For 1(d), 1(e) & 1(f), the diode is forward biased such that n p ( x p ) = 1015 cm −3 .
(d) [5 points] Calculate the applied voltage, VD.
VD = _______________
(e) [10 points] Calculate the ratio of electron current density to hole current density,
K=Je/Jh, in the p-quasi-neutral-region (p-QNR). Explain your reasoning. [You can
assume that xp << Wp and –xn << -Wn, that is, the widths of both SCR's are much
smaller than those of the QNR's]
K = _______________
4
(f) [10 points] Assume that for charge neutrality p′p ( x ) ≈ n′p ( x ) , where
p ' p = p p ( x) − p po and n' p = n p ( x) − nno . Since we are at Low Level Injection (LLI)
condition ⎡⎣ n p ( x p ) << p po ⎤⎦ , you can assume that p′p ( x p ) << p po . Calculate the
magnitude of the electric field in the p-quasi-neutral region (p-QNR). {Hint:
Remember that there is a concentration gradient for majority carriers too!}
E = _________________
5
Problem 2 [40 points]
A 3-terminal MOS structure is fabricated on a p-type silicon substrate with a n+-doped Si
gate (Nd=1020 cm-3); the gate material thermal equilibrium potential is φn+=0.55 V . The
substrate doping is Na=1017 cm-3, and the oxide thickness, tox=10 nm. The doping of the
n+ contact region is Nd=1020 cm-3.
VGB
-
VCB
G
-+
+
-
n+
C
n+
p
B
(a) [5 points] What is the value of the contact junction, n+-p, built-in potential, φJ?
φJ=______________
(b) [5 points] What is the value of the flatband voltage, VFB?
VFB=______________
6
(c) [15 points] With VCB1=0 V and VGB1=5V find the inversion charge density (charge
per unit area), q*N1.
q*N1 =_________________
7
(d) [15 points] A contact-to-body voltage, VCB2=3 V is applied. Find the gate-to-body
voltage VGB2 at which the magnitude of the channel charge is equal to its value for
VGB=5 V, VCB=0, i.e. q*N2 (VGB2, VCB=3V)= q*N1 (VGB1=5 V, VCB1=0). Explain
clearly.
VGB2=______________
8
Problem 3 [40 points]
You are given the multistage amplifier with device data shown below. Transistors M4,
M7, M9, and Q1 constitute the four amplifier stages and the rest of the transistors form the
bias circuitry. All MOSFETs are nominally biased in saturation and the BJT is in the
forward active region of operation. Also:
• Assume that the body of each MOSFET is connected to the source.
• For parts a – c, neglect channel length modulation, i.e. λ = 0, and basewidth
modulation, i.e. |VA| → ∞.
PMOS
NMOS
BJT
VTp = -0.7V
μpCox = 25μA/V2
λp = 0.05V-1
(W/L)p =40/2
VTn = 0.7V
μnCox = 50μA/V2
λn = 0.05V-1
(W/L)n = 20/2
βF = βo = 100
VA = | 20 |V
VCESAT = 0.2V
2.5 V
M6
M2
Q1
RS
M4
IREF
100 μA
vs
M8
+
−
vOUT
+ V
− BIAS
M1
M3
M7
M5
M9
M10
-2.5 V
9
(a) [5 points] Determine the current through each leg of the circuit i.e. the drain current
of M3, M5, M6, M9 and M10?.
ID3______________________
ID5______________________
ID6______________________
ID9______________________
ID10______________________
(b) [5 points] Determine VGS for M1 and VSG for M2.
VGS1=______________________
VSG2=______________________
10
(c) [10 points] Calculate the output resistance of the amplifier, Rout.
Rout=_______________
11
(d) [15 points] Calculate the voltage gain, Av0=vout/vin of the amplifier.
{hint: You must include the output resistance of supply current source transistors}
Av0=___________________
12
(e) [10 points] For this part you are also given that C*ox=3 fF/μm2, from which you can
calculate the gate-source capacitance, Cgs, of the MOSFETs. You are also given that the
gate-drain capacitance per unit width in saturation is C*gd=0.5 fF/ μm. Finally, the signal
source resistance is RS=10 Kohm. Of the three amplifiers based on transistors M4, M7,
and M8 determine the one that dominates the cutoff frequency, ωH, of the amplifier.
Make reasonable approximations and calculate that frequency.
ωH=____________________
13
6.012 Microelectronic Devices and Circuits
TQE, Spring 2008
Parameter Values:
Periodic Table:
q = 1.6x10−19 Coul
III
IV
V
εo = 8.854 x10−14 F/cm
B
C
N
Al
Ga
Si
Ge
P
As
In
Sn
Sb
εr,Si = 11.7, εSi ≈ 10−12 F/cm
εr,SiO = 3.9,
2
εSiO ≈ 3.5x10−13 F /cm
2
n i [[email protected] ] ≈ 10 cm −3
10
kT /q ≈ 0.025 V;
(kT /q) ln10 ≈ 0.06 V
1μm = 1x10−4 cm
Drift/Diffusion:
Drift velocity :
Conductivity :
Diffusion flux :
Einstein relation :
Electrostatics:
sx = ±μ m E x
σ = q(μ e n + μ h p)
∂C
Fm = −Dm m
∂x
Dm kT
=
μm
q
The Five Basic Equations:
Electron continuity :
Hole continuity :
Electron current density :
Hole current density :
Poisson's equation :
dE(x)
= ρ (x)
dx
dφ (x)
−
= E(x)
dx
d 2φ (x)
−ε
= ρ (x)
dx 2
ε
E(x) =
1
ε
∫ ρ(x)dx
φ (x) = − ∫ E(x)dx
φ (x) = −
1
ε
∫∫ ρ(x)dxdx
∂n(x,t) 1 ∂J e (x,t)
−
= gL (x,t) − [n(x,t) ⋅ p(x,t) − n i2 ]r(T)
q ∂x
∂t
∂p(x,t) 1 ∂J h (x,t)
+
= gL (x,t) − [n(x,t) ⋅ p(x,t) − n i2 ]r(T)
q ∂x
∂t
∂n(x,t)
J e (x,t) = qμ e n(x,t)E(x,t) + qDe
∂x
∂p(x,t)
J h (x,t) = qμ h p(x,t)E(x,t) − qDh
∂x
∂E(x,t) q
= [p(x,t) − n(x,t) + N d+ (x) − N a− (x)]
∂x
ε
Uniform doping, full ionization, TE
n - type, N d >> N a :
no ≈ N d − N a ≡ N D ,
po = n i2 n o ,
p - type, N a >> N d :
po ≈ N a − N d ≡ N A ,
n o = n i2 po ,
kT N D
ln
q
ni
kT N
φ p = − ln A
ni
q
φn =
14
Uniform optical excitation, uniform doping
n = n o + n'
p = po + p'
Low level injection, n',p' << p o + n o :
n' = p'
dn'
= gl (t) − (po + n o + n')n' r
dt
dn'
n'
+
= gl (t)
dt τ min
with τ min ≈ ( po r)
−1
Flow problems (uniformly doped quasi-neutral regions with quasi-static excitation and low
level injection; p-type example):
Minority carrier excess :
Minority carrier current density :
Majority carrier current density :
Electric field :
Majority carrier excess :
d 2 n'(x)
n'(x)
1
−
= −
gL (x)
2
2
Le
De
dx
dn'(t)
J e (x) ≈ qDe
dx
J h (x) = JTot − J e (x)
⎤
1 ⎡
Dh
E x (x) ≈
J e (x)⎥
⎢J h (x) −
qμ h po ⎣
De
⎦
ε dE x (x)
p'(x) ≈ n'(x) +
q dx
Le ≡ De τ e
Short base, infinite lifetime limit:
Minority carrier excess :
d 2 n'(x)
1
1
≈ −
gL (x), n'(x) ≈ −
2
dx
De
De
∫∫ g (x)dxdx
L
Non-uniformly doped semiconductor sample in thermal equilibrium
d 2φ (x)
q
= {n i [e qφ (x ) kT − e−qφ (x ) kT ]− [N d (x) − N a (x)]}
2
dx
ε
n o (x) = n ie qφ (x ) kT , po (x) = n ie−qφ (x ) kT , po (x)n o (x) = n i2
15
Depletion approximation for abrupt p-n junction:
⎧ 0
⎪
⎪−qN Ap
ρ(x) = ⎨
⎪ qN Dn
⎪⎩ 0
for
x < −x p
for −x p < x < 0
for 0 < x < x n
xn < x
for
N Ap x p = N Dn x n
2εSi (φ b − v AB ) (N Ap + N Dn )
q
N Ap N Dn
w(v AB ) =
2q (φ b − v AB )
E pk =
εSi
qDP (v AB ) = −AqN Ap x p (v AB ) = −A 2qεSi (φ b − v AB )
Ideal p-n junction diode i-v relation:
n i2 qv AB / kT
n i2 qv AB / kT
n(-x p ) =
e
, n'(-x p ) =
−1);
(e
N Ap
N Ap
⎡ D
De ⎤ qv AB / kT
h
iD = Aq n i2 ⎢
+
-1]
⎥ [e
⎣ N Dn w n,eff N Ap w p,eff ⎦
-x p
qQNR,p -side = Aq
∫
qQNR,n -side = Aq ∫ p'(x)dx,
-w p
N Ap N Dn
(N
Ap
+ N Dn )
N Ap N Dn
(N
Ap
+ N Dn )
n i2 qvAB / kT
n i2 qv AB / kT
p(x n ) =
e
, p'(x n ) =
−1)
(e
N Dn
N Dn
⎧
wm − x m
if L m >> w m
⎪
w m,eff = ⎨ Lm tanh [(w m − x m ) Lm ] if L m ~ w m
⎪
Lm
if L m << w m
⎩
wn
n'(x)dx,
kT N Dn N Ap
ln
n i2
q
φb ≡ φn − φ p =
Note : p'(x) ≈ n'(x) in QNRs
xn
Ebers-Moll Model for Bipolar Junction Transistor (BJT) Characteristics:
(npn; no base width modulation)
iE (v BE ,v BC ) = − IES (e qvBE / kT −1) + α R ICS (e qvBC / kT −1)
iC (v BE ,v BC ) = α F IES (e qvBE / kT −1) − ICS (e qvBC / kT −1)
with :
⎛ D
⎛ D
De ⎞
De ⎞
h
h
IES ≡ Aqn i2 ⎜⎜
+
+
⎟⎟, ICS ≡ Aqn i2 ⎜⎜
⎟⎟,
⎝ N DE w E ,eff N AB w B,eff ⎠
⎝ N DC wC ,eff N AB w B,eff ⎠
αF ≡
(1− δB ) , α ≡ (1− δB ) , δ
(1+ δE ) R (1+ δC ) E
≡
w2
w
Dh N AB w B ,eff
D N
⋅
⋅
, δB ≡ B,eff
, δC ≡ h ⋅ AB ⋅ B ,eff
2
De N DE w E ,eff
2Le
De N DC wC ,eff
Large signal BJT Model in Forward Active Region (FAR):
(npn with base width modulation)
iB (v BE ,vCE ) = IBS (e qvBE / kT −1)
iC (v BE ,v BC ) = β F iB (v BE ,vCE )[1+ λvCE ] = β F IBS (e qv BE / kT −1)[1+ λvCE ]
with :
IBS ≡
IES
Aqn i2 ⎛ Dh
De ⎞
=
+
⎜⎜
⎟,
(β F + 1) (β F + 1) ⎝ N DE wE ,eff N AB wB,eff ⎟⎠
βF ≡
αF
, and
(1− α F )
λ≡
1
VA
16
MOS Capacitor:
Flat - band voltage : VFB ≡ vGB at which φ (0) = φ p−Si
VFB = φ p−Si − φ m
Threshold voltage : VFB ≡ vGC at which φ (0) = − φ p−Si + v BC
VT (v BC ) = VFB − 2φ p−Si +
{
[
1
2εSi qN A 2φ p−Si − v BC
*
Cox
x DT (v BC ) =
Depletion region width at threshold :
*
Cox
=
Oxide capacitance per unit area :
]}
1/ 2
[
2εSi 2φ p−Si − v BC
]
qN A
εox
[ε
t ox
r,SiO2
= 3.9,
εSiO ≈ 3.5x10−13 F /cm]
2
*
q*N = −Cox
[vGC − VT (v BC )]
Inversion layer sheet charge density :
Accumulation layer sheet charge density :
*
q*P = −Cox
[vGB − VFB )]
Gradual Channel Appoximation for MOSFET Characteristics:
(n-channel; no channel length modulation)
with VT (v BS ) ≡ VFB − 2φ p−Si +
W
*
K ≡ μe Cox
,
L
{
[
1
2εSiqN A 2φ p−Si − v BS
*
Cox
*
Cox
≡
εox
t ox
,
]} ,
1/ 2
⎧
1 ⎪
εSiqN A
α ≡ 1+ * ⎨
Cox ⎪ 2 2φ p−Si − v BS
⎩
[
Good only for v BS ≤ 0, and v DS ≥ 0 :
iG (vGS ,v DS ,v BS )
⎧
0
for
⎪
⎪⎪
K
2
iD (vGS ,v DS ,v BS ) = ⎨
for
[vGS − VT (v BS )]
2α
⎪
⎪ K ⎧⎨v − V (v ) − α v DS ⎫⎬ v
for
T
BS
DS
⎪⎩ ⎩ GS
2 ⎭
= 0,
1
α
⎫
⎪
⎬
⎪⎭
1/ 2
]
iB (vGS ,v DS ,v BS ) = 0
[vGS − VT (v BS )] < 0 < v DS
0<
1
α
[vGS − VT (v BS )] < v DS
0 < v DS <
1
α
[vGS − VT (v BS )]
Note: α is typically assumed to be equal to 1 (i.e. α=1) unless otherwise stated. Large Signal MOSFET Model in Saturation (FAR):
(n-channel with channel length modulation)
1
When v BS ≤ 0, vGS ≥ VT (v BS ), and v DS ≥ [vGS − VT (v BS )] :
α
iG (vGS ,v DS ,v BS ) = 0,
iB (vGS ,v DS ,v BS ) = 0
K
2
iD (vGS ,v DS ,v BS ) =
[vGS − VT (v BS )] [1+ λ(v DS − v DS,sat )]
2α
with λ ≡
1
VA
17
Small Signal Linear Equivalent Circuits:
•
p-n Diode (n+-p doping assumed for Cd)
gd ≡
∂iD
∂v AB
=
Q
q
q ID
IS e qVAB / kT ≈
,
kT
kT
Cd = Cdp + Cdf ,
qεSi N Ap
where Cdp (VAB ) = A
,
2 (φ b − VAB )
•
BJT (in FAR)
q
gm =
β o IBS e qVBE
kT
go = β o IBS [e qVBE
kT
kT
[1+ λVCE ]
≈
+ 1] λ ≈ λ IC
q I [w p − x p ]
and Cdf (VAB ) = D
= gd τ d
kT
2De
2
q IC
,
kT
⎛
IC ⎞
⎜ or ≈
⎟
VA ⎠
⎝
Cπ = gm τ b + B-E depletion cap. with τ b ≡
•
gπ =
w B2
,
2De
gm
βo
=
with τ d
[w
≡
− xp]
2
p
2De
q IC
β o kT
Cμ : B-C depletion cap.
MOSFET (in saturation)
gm = K [VGS − VT (VBS )][1+ λVDS ] ≈ K [VGS − VT (VBS )] =
go =
K
2
[VGS − VT (VBS )] λ ≈ λ ID
2
gmb = η gm = η 2K ID
2K ID = 2ID [VGS − VT (VBS )]
⎛
ID ⎞
⎜ or ≈
⎟
VA ⎠
⎝
with η ≡ −
∂VT
∂v BS
=
Q
1
*
Cox
εSiqN A
qφ p − VBS
2
*
Cgs = W L Cox
,
Csb ,Cgb ,Cdb : depletion capacitances
3
*
*
, where Cgd
is the G-D fringing and overlap capacitance per unit gate length (parasitic)
Cgd = W Cgd
18
Single transistor analog circuit building block stages
BIPOLAR
Voltage
Current
Input
Output
gain, Av
gain, Ai
β gl
−
[g o + g l ]
resistance, Ri
resistance, Ro
⎛ 1 ⎞
⎟⎟
ro ⎜⎜ =
⎝ go ⎠
(
)
gm
≈ − g m rl'
[g o + g l ]
gm
≈ g r'
Common base
[g o + g l ] m l
[g m + g π ] ≈ 1
Emitter follower
[g m + g π + g o + g l ]
r
≈− l
Emitter degeneracy
RF
[g − G F ] ≈ − g R
− m
Shunt feedback
m F
[g o + G F ]
Common emitter
−
(
MOSFET
Common source
Common gate
−
)
rπ
≈1
β gl
≈
[g o + g l ]
≈
≈ rπ + [β + 1]R F
≈β
−
rπ + [β + 1]rl'
≈β
≈ [β + 1]ro
rπ
[β + 1]
gl
GF
1
g π + G F [1 − Av ]
R
1
+ S
β
gm
≈ ro
⎛
1
ro || R F ⎜⎜ =
⎝ g o + GF
Voltage
Current
Input
Output
gain, Av
gain, Ai
resistance, Ri
∞
∞
resistance, Ro
⎛ 1 ⎞
⎟⎟
ro ⎜⎜ =
⎝ go ⎠
⎧ [g + g mb + g o ]⎫
≈ ro ⎨1 + m
⎬
gt
⎩
⎭
1
1
≈
[g m + g o + gl ] g m
(
gm
= − g m rl'
[go + gl ]
)
≈ [g m + g mb ]rl'
≈1
gm
≈1
[g m + go + gl ]
Source degeneracy
r
≈− l
(series feedback)
RF
[g − GF ] ≈ − g R
Shunt feedback
− m
m F
[go + GF ]
Source follower
−
1
[g m + g mb ]
≈
∞
∞
∞
∞
≈ ro
gl
GF
1
GF [1 − Av ]
⎛
⎞
1
⎟⎟
ro || RF ⎜⎜ =
[
]
g
G
+
o
F ⎠
⎝
⎞
⎟⎟
⎠
OCTC/SCTC Methods for Estimating Amplifier Bandwidth
⎡
⎤
⎡
⎤
−1
≤ ⎢∑ [ω i ] ⎥ = ⎢∑ RiCi ⎥
⎣ i
⎦
⎣ i
⎦
-1
OCTC estimation of ω HI:
ω HI
-1
with Ri defined as the equivalent resistance in parallel with Ci with all other parasitic
device capacitors (Cπ's, Cµ's, Cgs's, Cgd's, etc.) open circuited.
SCTC estimation of ω LO:
ω LO ≥
∑ω = ∑ [R C ]
−1
j
j
j
j
j
with Rj defined as the equivalent resistance in parallel with Cj with all other baising
and coupling capacitors (CΙ's, CO's, CE's, CS's, etc.) short circuited.
19
Difference- and Common-mode signals
Given two signals, v1 and v2, we can decompose them into two new signals, one (vC)
that is common to both v1 and v2, and the other (vD) that makes an equal, but opposite
polarity contribution to v1 and v2:
v
v
[v + v ]
v D ≡ v1 − v 2 and vC ≡ 1 2
⎯
⎯→
v1 = vC + D and v1 = vC − D
2
2
2
CMOS Performance
Transfer characteristic:
In general : VLO = 0,
VLO = VDD ,
ION = 0,
IOFF = 0
V
Symmetry : VM = DD and NM LO = NM HI ⇒ K n = K p and VTp = VTn
2
Minimum size gate : Ln = L p = Lmin , W n = W min , W p = (μn μ p )W n
Switching times and gate delay:
τ Ch arg e = τ Disch arg e =
2CLVDD
2
K n [VDD − VTn ]
*
*
CL = n(W n Ln + W p L p )Cox
= 3nW min Lmin Cox
τ Min.Cycle = τ Ch arg e + τ Disch arg e
assumes μe = 2μh
12nL2minVDD
=
2
μe [VDD − VTn ]
Power dissipation:
Pave @ Max. f = CLV
2
DD
f max ∝
2
CLVDD
τ Min.Cycle
μeW minεoxVDD [VDD − VTn ]
2
∝
t ox Lmin
Pave@Max. f
P
μ ε V [V − VTn ]
=
∝ ave@Max. f ∝ e ox DD 2DD
InverterArea W min Lmin
t ox Lmin
2
PDave @ Max. f
Device transit times:
Short Base Diode transit time : τ b =
w B2
w B2
=
2Dmin,B 2μmin,BVthermal
Channel transit time w.o. velocity saturation : τ Ch
L2
2
=
3 μCh VGS − VT
Channel transit time with velocity saturation : τ Ch =
L
ssat
20