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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 13: September 26, 2014 Variation 1 Penn ESE370 Fall2014 -- DeHon Previously • Understand how to model transistor behavior • Given that we know its parameters – Vdd, Vth, tOX, COX, W, L, NA … CGC CGCS CGCB 2 Penn ESE370 Fall2014 -- DeHon But… • We don’t know its parameters (perfectly) 1.Fabrication parameters have error range 2.Identically drawn devices differ 3.Parameters change with environment (e.g. Temperature) 4.Parameters change with time (aging) Why I am more concerned with robustness than precision. 3 Penn ESE370 Fall2014 -- DeHon Today • Sources of Variation – Fabrication – Operation – Aging • Coping with Variation – Margin – Corners – Binning 4 Penn ESE370 Fall2014 -- DeHon Fabrication 5 Penn ESE370 Fall2014 -- DeHon Variation Types • Many reasons why things are different – Show up in many different ways. • Scales – Wafer-to-wafer, die-to-die, transistor-totransistor • Correlations – Systematic, spatial, random (uncorrelated) 6 Penn ESE370 Fall2014 -- DeHon Source: Noel Menezes, Intel ISPD2007 7 Penn ESE370 Fall2014 -- DeHon Process Shift • • • • Oxide thickness Doping level Layer alignment Growth and Etch rates and times – Depend on chemical concentrations • How precisely can we control those? • Vary machine-to-machine, day-to-day • Impact all transistors on wafer 8 Penn ESE370 Fall2014 -- DeHon Systematic Spatial • Parameters change consistently across wafer or chip based on location • Chemical-Mechanical Polishing (CMP) – Dishing • Lens distortion 9 Penn ESE370 Fall2014 -- DeHon FPGA Systematic Variation • 65nm • Virtex 5 Penn ESE370 Fall2014 -- DeHon [Tuan et al. / ISQED 2010] 10 Oxide Thickness [Asenov et al. TRED 2002] 11 Penn ESE370 Fall2014 -- DeHon Line Edge Roughness • 1.2mm and 2.4mm lines From: http://www.microtechweb.com/2d/lw_pict.htm 12 Penn ESE370 Fall2014 -- DeHon Optical Sources • What is the shortest wavelength of visible light? • How compare to 22nm feature size? 13 Penn ESE370 Fall2014 -- DeHon Phase Shift Masking Today’s chips use λ=193nm Source http://www.synopsys.com/Tools/Manufacturing/MaskSynthesis/PSMCreate/Pages/default.aspx 14 Penn ESE370 Fall2014 -- DeHon Line Edges (PSM) Source: http://www.solid-state.com/display_article/122066/5/none/none/Feat/Developments-in-materials-for-157nm-photoresists 15 Penn ESE370 Fall2014 -- DeHon Intel 65nm SRAM (PSM) Source: http://www.intel.com/technology/itj/2008/v12i2/5-design/figures/Figure_5_lg.gif 16 Penn ESE370 Fall2014 -- DeHon Statistical Dopant Placement 17 Penn ESE370 Fall2014 -- DeHon [Bernstein et al, IBM JRD 2006] Random Trans-to-Trans • • • • Random dopant fluctuation Local oxide variation Line edge roughness Etch and growth rates – Stochastic process • Transistors differ from each other in random ways Penn ESE370 Fall2014 -- DeHon 18 Source: Noel Menezes, Intel ISPD2007 19 Penn ESE370 Fall2014 -- DeHon Impact • Changes parameters – W, L, tOX, Vth • Change transistor behavior – W? – L? – tOX? IDS IDS VDSAT satCOX W VGS VT 2 2 W VDS mnCOX VGS VT VDS L 2 20 Penn ESE370 Fall2014 -- DeHon Example: Vth • Many physical effects impact Vth – Doping, dimensions, roughness • Behavior highly dependent on Vth IDS IDS VDSAT satCOX W VGS VT 2 W IS e L Penn ESE370 Fall2014 -- DeHon VGS VT nkT / q VDS kT / q 1 e 1 VDS 21 Vth Variability @ 65nm 22 Penn ESE370 Fall2014 -- DeHon [Bernstein et al, IBM JRD 2006] Impact of Vth Variation? • Higher Vth? – Not drive as strongly – Id,vsat (Vgs-Vth) – Performance? 23 Penn ESE370 Fall2014 -- DeHon Impact Performance • Vth Ids Delay (Ron * Cload) 24 Penn ESE370 Fall2014 -- DeHon Impact of Vth Variation? • Lower Vth? – Not turn off as well leaks more IDS W IS e L Penn ESE370 Fall2014 -- DeHon VGS VT nkT / q VDS kT / q 1 e 1 VDS 25 2004 Borkar (Intel) Micro 37 (2004) Penn ESE370 Fall2014 -- DeHon 26 Operation Temperature Voltage 27 Penn ESE370 Fall2014 -- DeHon Temperature Changes • Different ambient environments – January in Maine – July in Philly – Air conditioned machine room • Self heat from activity of chip • Quality of heat sink (attachment thereof) IDS W IS e L Penn ESE370 Fall2014 -- DeHon VGS VT nkT / q VDS kT / q 1 e 1 VDS 28 Self Heating Borkar (Intel) Micro 37 (2004) 29 Penn ESE370 Fall2014 -- DeHon Thermal Profile for Processor 30 Penn ESE370 Fall2014 -- DeHon [Reda/IEEE Tr Emerging CAS v1n2 2011] How does temperature impact on-current? • High temperature – More free thermal energy • Easier to conduct • Lowers Vth – Increase rate of collision • Lower saturation velocity • Lower saturation voltage • Lower peak Ids slows down • One reason don’t want chips to run hot 31 Penn ESE370 Fall2014 -- DeHon Temperature and Ids 32 Penn ESE370 Fall2014 -- DeHon How does temperature impact leakage current? • High temperature Lowers Vth IDS W IS e L Penn ESE370 Fall2014 -- DeHon VGS VT nkT / q VDS kT / q 1 e 1 VDS 33 Voltage • Power supply isn’t perfect • Differs from design to design – Board to board? – How precise is regulator? • IR-drop in distribution • Bounce with current spikes 34 Penn ESE370 Fall2014 -- DeHon Aging Hot Carrier NBTI 35 Penn ESE370 Fall2014 -- DeHon Hot Carriers • Trap electrons in oxide – Also shifts Vth 36 Penn ESE370 Fall2014 -- DeHon NBTI • Negative Bias Temperature Instability – Interface traps, Holes • Long-term negative gate-source voltage – Affects PFET most • Increase Vth • Partially recoverable? • Temperature dependent Another reason not to run hot. Penn ESE370 Fall2014 -- DeHon [Stott, FPGA2010] 37 Measured Accelerated Aging (Cyclone III, 65nm FPGA) Penn ESE370 Fall2014 -- DeHon [Stott, FPGA2010] 38 Coping with Variation 39 Penn ESE370 Fall2014 -- DeHon Variation • See a range of parameters – L: Lmin – Lmax – Vth: Vth,min – Vth,max 40 Penn ESE370 Fall2014 -- DeHon Impact of Vth Variation • Higher VTH – Not drive as strongly – Id,vsat (Vgs-VTH) • Lower VTH IDS VDSAT satCOX W VGS VT 2 – Not turn off as well leaks more W IDS IS e L Penn ESE370 Fall2014 -- DeHon VGS VT nkT / q VDS kT / q 1 e 1 VDS 41 Variation • Margin for expected variation • Must assume Vth can be any value in range – Speed assume Vth slowest value Ion,min=Ion(Vth,max) Probability Distribution Id,vsat (Vgs-Vth) VTH 42 Penn ESE370 Fall2014 -- DeHon Gaussian Distribution From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg 43 Penn ESE370 Fall2014 -- DeHon Impact • Given – Vth,nom = 250mV – Sigma 25mV • Probability of 100 transistor circuit in range when each has 96% prob. ? • …when each has 99.8% probability? 44 Penn ESE370 Fall2014 -- DeHon Gaussian Distribution From: http://en.wikipedia.org/wiki/File:Standard_deviation_diagram.svg 45 Penn ESE370 Fall2014 -- DeHon Variation • See a range of parameters – L: Lmin – Lmax – Vth: Vth,min – Vth,max • Validate design at extremes – Work for both Vth,min and Vth,max ? – Design for worst-case scenario 46 Penn ESE370 Fall2014 -- DeHon Margining • Also margin for – Temperature – Voltage – Aging: end-of-life 47 Penn ESE370 Fall2014 -- DeHon Process Corners • Many effects independent • Many parameters • With N parameters, – Look only at extreme ends (low, high) – How many cases? • Try to identify the {worst,best} set of parameters – Slow corner of design space, fast corner • Use corners to bracket behavior Penn ESE370 Fall2014 -- DeHon 48 Simple Corner Example What happens at various corners? 350mV Vthp 150mV 150mV 350mV Vthn 49 Penn ESE370 Fall2014 -- DeHon Process Corners • Many effects independent • Many parameters • Try to identify the {worst,best} set of parameters – E.g. Lump together things that make slow • Vthn, Vthp, temperature, Voltage • Try to reduce number of unique corners – Slow corner of design space • Use corners to bracket behavior 50 Penn ESE370 Fall2014 -- DeHon Range of Behavior Probability Distribution • Still get range of performances • Any way to exploit the fact some are faster? Delay 51 Penn ESE370 Fall2014 -- DeHon Probability Distribution Speed Binning Sell Premium Sell Sell nominal cheap Discard Delay 52 Penn ESE370 Fall2014 -- DeHon Idea • Parameters Approximate • Differ – Chip-to-chip, transistor-to-transistor, over time • Robust design accommodates – Tolerance and Margins – Doesn’t depend on precise behavior Penn ESE370 Fall2014 -- DeHon 53 Midterm 1 • Contents should not be a surprise – Identify CMOS/non-CMOS – Identify CMOS function – Any logic function CMOS gate – Noise Margins / Restoration – Circuit quasistatic configuration and switching delay 54 Penn ESE370 Fall2014 -- DeHon Admin • Midterm Monday – 7—9pm in Towne 303 • Previous midterm – Solutions linked to 2010--2013 syllabus • But only one midterm in 2010 so parts more advanced than where we are now • Review on Sunday – Poll time 55 Penn ESE370 Fall2014 -- DeHon