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Semiconductor Device Modeling and Characterization – EE5342 Lecture 35 – Spring 2011 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc/ Flat-band parameters for p-channel (n-subst) n substrate : VFB ms Q'ss (no change) C'Ox Ox C'Ox , Q'ss is the Ox/Si chg den xOx For a p poly - Si gate, s m s NvNd Eg Nd ms Vt ln 2 Vt ln 0 ni 2q ni ©rlc L35-29Apr2011 Eg q Fully biased pchannel VT calc n substrate : VG, at threshold VT VT VC VFB 2n Q'd,max C'Ox VFB V Nd n Vt ln 0, Q'd,max qNdxd,max , ni 22 n VC VB xd,max , V 0 qNd ©rlc L35-29Apr2011 p-channel VT for VC = VB = 0 Fig 10.21* ©rlc L35-29Apr2011 Ion implantation ©rlc L35-29Apr2011 “Dotted box” approx ©rlc L35-29Apr2011 Nimpl dx NaiXi 0 area under area under dotted dashed curve ' Qss curve Na qNaiXi , F NaiX Nd di di Xi Xd, max ' Qss , before impl To get Vt as desired, implant Nai Xi qNaiXi to get Vt 2.43, etc ' Cox ©rlc L35-29Apr2011 Mobilities ©rlc L35-29Apr2011 Differential charges for low and high freq high freq. From Fig 10.27* ©rlc L35-29Apr2011 Ideal low-freq C-V relationship ©rlc L35-29Apr2011 Fig 10.25* Comparison of low and high freq C-V Fig 10.28* ©rlc L35-29Apr2011 Effect of Q’ss on the C-V relationship Fig 10.29* ©rlc L35-29Apr2011 n-channel enhancement MOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 n+ Depl Reg ©rlc L35-29Apr2011 e-e- e- e- e- p-substrate VB < 0 n+ Acceptors Conductance of inverted channel • • • • • Q’n = - C’Ox(VGC-VT) n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) The conductivity sn = (n’s/t) q mn G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’sqmnW) L VD 0 VS I dL C'Ox VG VC VT mnWdV ©rlc L35-29Apr2011 Basic I-V relation for MOS channel WmnCOx 2 ID 2VG VT VDS VDS , VDS VG VT 2L At VDS VDS,sat VG VT , Q'n y L 0 Sat. so let ID be given by ID VDS,sat , for VDS VDS,sat VG VT so ID ID,sat WmnCOx VG VT 2 2L ©rlc L35-29Apr2011 I-V relation for n-MOS (ohmic reg) m C' W 2 ID 2VG VT VDS VDS . Note for 2 L ohmic VDS VG VT VDS,sat , ID non-physical result is non - physical. ID,sat At VDS,sat , n's,y L 0 n Ox assume that channel curr. is const for VDS VDS,sat ID,sat mnC'Ox W VGS VT 2 2 L ©rlc L35-29Apr2011 saturated VDS,sat VDS Universal drain characteristic mnC'Ox W ID1 1V 2 2 L ID VGS=VT+3V 9ID1 ohmic 4ID1 ID1 ©rlc L35-29Apr2011 mnC'Ox W 2 ID,sat VDS 2 L saturated, VDS>VGS-VT VGS=VT+2V VGS=VT+1V VDS Characterizing the n-ch MOSFET VD ID ID D G S slope B mnC'Ox W L 2 VDS VGS , VT 0 VDS VGS VT , so mn C'Ox W VGS VT 2 ID,sat 2 L ©rlc L35-29Apr2011 VT VGS Low field ohmic characteristics mnC'Ox W 2 ID 2VGS VT VDS VDS , 2 L for ohmic region. Furthermore, let VDS VG VT , so that W ID mnC'Ox VGS VT VDS L W KP VGS VT VDS , KP mnC'Ox L dID W KP VDS dV L GS V V V DS G ©rlc L35-29Apr2011 T MOSFET Device Structre Fig. 4-1, M&A* ©rlc L35-29Apr2011 4-7a (A&M) ©rlc L35-29Apr2011 Figure 4-7b ©rlc L35-29Apr2011 (A&M) Figure 4-8a ©rlc L35-29Apr2011 (A&M) Figure 4-8b ©rlc L35-29Apr2011 (A&M) Body effect data Fig 9.9** ©rlc L35-29Apr2011 MOSFET equivalent circuit elements Fig 10.51* Cgs 2 1 COx , Cgd COx , COx WLC'Ox 3 3 ©rlc L35-29Apr2011 n-channel enh. circuit model G RG S RB Cgs RDS Cgd Cbs Idrain DSS DSD Cbd RB ©rlc L35-29Apr2011 B RD D Cgb MOS small-signal equivalent circuit Fig 10.52* ©rlc L35-29Apr2011 MOSFET circuit parameters Transcondu c tan ce ID gm VGS V DS Wmn C'Ox VGS VT , saturation gms L Wmn C'Ox gmL VDS, ohmic region L ©rlc L35-29Apr2011 MOSFET circuit parameters (cont) Output or drain conductance ID gd VDS V GS gds 0, saturation gdL WmnC'Ox VGS VT VDS , ohmic L ©rlc L35-29Apr2011 Substrate bias effect on VT (body-effect) Letting VT calculation be relative to Source VT VS VFB 2 p xd,max VT VSB qNa xd,max 2 2 p VSB qNa 2 SiqNa 0 C'Ox ©rlc L35-29Apr2011 C'Ox , where , so VT VT VSB 2 p VSB 2 p Body effect data Fig 9.9** ©rlc L35-29Apr2011 Fully biased nchannel VT calc p substrate : VG, at threshold VT VT Vs VFB 2p Q'd,max VFB V C'Ox ni p Vt ln 0, Q'd,max qNa xd,max , Na xd,max ©rlc L35-29Apr2011 2 2 p VB Vs qNa , V 0 Values for ms with silicon gate n poly to p - Si : ms NCNa Si Si Vt ln 2 ni NCNa Eg Na Note : Vt ln 2 Vt ln ni ni 2q Eg NC p poly to n - Si : ms Si Si Vt ln q Nd NC Eg Nd Note : Vt ln Vt ln ni Nd 2q ©rlc L35-29Apr2011 ©rlc L35-29Apr2011 Fig 8.11** |Q’d,max|/q (cm-2) xd,max (microns) Q’d,max and xd,max for biased MOS capacitor I-V relation formn-MOS C' W 2 ID 2VG VT VDS VDS . Note for 2 L ohmic VDS VG VT VDS,sat , ID non-physical result is non - physical. ID,sat At VDS,sat , n's,y L 0 n Ox assume that channel curr. is const for VDS VDS,sat ID,sat mnC'Ox W VGS VT 2 2 L ©rlc L35-29Apr2011 saturated VDS,sat VDS MOS channellength modulation Fig 11.5* ©rlc L35-29Apr2011 Analysis of channel length modulation Assume the DR change the channel L length modulation, so I'D ID L L 2Si L 2 p VDS,sat VDS qNa 2 p VDS,sat , VDS VDS VDS,sat mn C'Ox W VGS VT 2 1 VDS ID,sat 2 L ©rlc L35-29Apr2011 References • CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995. • M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. • **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. • *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997 ©rlc L35-29Apr2011