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Properties of Complementary CMOS
Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
2
1
B
Introduction to VLSI Design
2 C
2
Introduction
© Steven P. Levitan 1998
Propagation Delay Analysis - The Switch
Model
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
What is the Value of Ron?
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Numerical Examples of Resistances for 1.2mm
CMOS
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
D
A
2
1
B
2C
2
Here it is assumed that Rp = Rn
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Influence of Fan-In and Fan-Out
on Delay
VDD
A
C
B
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
D
t
Introduction to VLSI Design
p
= a FI + a FI 2 + a FO
1
2
3
Introduction
© Steven P. Levitan 1998
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design
Techniques
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Introduction to VLSI Design
Distributed RC-line
Can Reduce Delay with more than 30%!
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(2)
• Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
Introduction to VLSI Design
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(3)
• Improved Logic Design
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(4)
• Buffering: Isolate Fan-in from Fan-out
CL
CL
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
A
B
Co = AB + C i(A+B)
28 transistors
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
A Revised Adder Circuit
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
A
B
B
Ci
A
B
24 transistors
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Properties of Complementary CMOS
Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
2
1
B
Introduction to VLSI Design
2 C
2
Introduction
© Steven P. Levitan 1998
Propagation Delay Analysis - The Switch
Model
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
What is the Value of Ron?
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Numerical Examples of Resistances for 1.2mm
CMOS
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
D
A
2
1
B
2C
2
Here it is assumed that Rp = Rn
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Influence of Fan-In and Fan-Out
on Delay
VDD
A
C
B
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
D
t
Introduction to VLSI Design
p
= a FI + a FI 2 + a FO
1
2
3
Introduction
© Steven P. Levitan 1998
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design
Techniques
• Transistor Sizing:
As long as Fan-out Capacitance dominates
• Progressive Sizing:
Out
InN
MN
CL
M1 > M2 > M3 > MN
In3
M3
C3
In2
M2
C2
In1
M1
C1
Introduction to VLSI Design
Distributed RC-line
Can Reduce Delay with more than 30%!
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(2)
• Transistor Ordering
critical path
critical path
CL
In3
M3
In2
M2
C2
In1
M1
C1
(a)
Introduction to VLSI Design
CL
In1
M1
In2
M2
C2
In3
M3
C3
(b)
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(3)
• Improved Logic Design
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Fast Complex Gate - Design Techniques
(4)
• Buffering: Isolate Fan-in from Fan-out
CL
CL
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Example: Full Adder
VDD
VDD
Ci
A
A
B
B
A
B
Ci
A
B
VDD
X
Ci
Ci
A
S
Ci
A
B
B
VDD
A
B
Ci
Co
A
B
Co = AB + C i(A+B)
28 transistors
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
A Revised Adder Circuit
V DD
VDD
A
B
A
V DD
A
B
B
Ci
B
Kill
"0"-Propagate
A
Ci
Ci
Co
S
Ci
A
"1"-Propagate
Generate
A
B
A
B
B
Ci
A
B
24 transistors
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Ratioed Logic
VDD
Resistive
Load
VDD
Depletion
Load
RL
PDN
VSS
(a) resistive load
PMOS
Load
VSS
VT < 0
F
In1
In2
In3
VDD
F
In1
In2
In3
PDN
VSS
(b) depletion load NMOS
F
In1
In2
In3
PDN
VSS
(c) pseudo-NMOS
Goal: to reduce the number of devices over complementary CMOS
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Ratioed Logic
VDD
• N transistors + Load
Resistive
Load
• VOH = V DD
RL
• VOL =
F
In1
In2
In3
RPN + RL
• Assymetrical response
PDN
• Static power consumption
• tpL= 0.69 RLCL
VSS
Introduction to VLSI Design
RPN
Introduction
© Steven P. Levitan 1998
Active Loads
VDD
Depletion
Load
VDD
PMOS
Load
VT < 0
VSS
F
In1
In2
In3
In1
In2
In3
PDN
VSS
PDN
VSS
depletion load NMOS
Introduction to VLSI Design
F
pseudo-NMOS
Introduction
© Steven P. Levitan 1998
Load Lines of Ratioed Gates
IL(Normalized)
1
Current source
0.75
0.5
Pseudo-NMOS
Depletion load
0.25
Resistive load
0
0.0
Introduction to VLSI Design
1.0
2.0
3.0
Vout (V)
Introduction
4.0
5.0
© Steven P. Levitan 1998
Pseudo-NMOS
VDD
A
B
C
D
F
CL
VOH = VDD (similar to complementary CMOS)
2
V OL
kp


2
k n  VDD – V Tn  V OL – -------------  = ------  V DD – VTp 
2 
2

kp
V OL =  VDD – V T  1 – 1 – -----(assuming that V T = V Tn = VTp )
kn
SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!!
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Psudo-NMOS
–
–
–
–
N+1 transistors (small) One pull-up P transistor
Ratio based logic: Sizes Matter
Sensitive to power supply
Static power dissipation: Slow and/or power hungry
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Pseudo-NMOS NAND Gate
VDD
GND
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Improved Loads
VDD
M1
Enable
M2
M1 >> M2
F
A
B
C
D
CL
Adaptive Load
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Improved Loads (2)
VDD
VDD
M1
M2
Out
A
A
B
B
Out
PDN1
PDN2
VSS
VSS
Dual Cascode Voltage Switch Logic (DCVSL)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Example
Out
Out
B
B
A
B
B
A
XOR-NXOR gate
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
NMOS-only switch
C=5V
C=5V
M2
A=5V
A=5V
B
Mn
B
M1
CL
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes
static power consumption
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Solution 1: Transmission Gate
C
A
C
A
B
B
C
C
C=5 V
A=5V
B
CL
C=0V
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Pass Gate Structures
Bad
Good
– Can be slow
– Complementary layout is
hard to do well
– Well plugs are a problem
(no vdd/gnd)
– Non-standard
minimization techniques
– True and complement
inputs typically needed.
Introduction to VLSI Design
Introduction
– Can be very small
– Complementary layout
not always used
– Non-Boolean logic
functions
– True switching
functions supported
– Storage integrated into
logic structures
© Steven P. Levitan 1998
Pass Logic

NMOS style - accept weak "1"'s
– restore good 1's with an inverter

CMOS style -- messy to lay out
– wells and well plugs

Precharged / feedback / pseudo-pullup
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
R (Ohm)
20000.0
Rp
10000.0
0.0
0.0
Req
1.0
2.0
3.0
4.0
5.0
Vout
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
Introduction to VLSI Design
Introduction
In2
© Steven P. Levitan 1998
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Delay in Transmission Gate Networks
5
5
V1
In
5
Vi
Vi-1
C
0
5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
Vn
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
CC
C
(c)
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Elmore Delay (Chapter 8)
Vin
R1
C1
1
R2
Ri-1
2
C2
i-1
Ci-1
Ri
i
Ci
RN
N
CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N
N =
Introduction to VLSI Design
N
N
i
 Ri  Cj =  C i  R j
i=1 j=i
i=1 j=1
Introduction
© Steven P. Levitan 1998
Delay Optimization
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
B
VDD
A
P
Co Carry Generation
Ci
A
P
Setup
Introduction to VLSI Design
S Sum Generation
Ci
P
Ci
VDD
Introduction
© Steven P. Levitan 1998
(2) NMOS Only Logic: Level Restoring
Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Level Restoring Transistor
5.0
with
5.0
3.0
VB
1.0
-1.00
without
3.0
with
VX
Vout (V)
without
2
t (nsec)
1.0
4
6 -1.00
4
6
t (nsec)
(a) Output node
Introduction to VLSI Design
2
(b) Intermediate node X
Introduction
© Steven P. Levitan 1998
Solution 3: Single Transistor Pass Gate with
VT=0
VDD
VDD
0V
5V
VDD
0V
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
Complimentary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
Introduction to VLSI Design
A
F=AÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
Introduction
A
F=AÝ
EXOR/NEXOR
© Steven P. Levitan 1998
Pass Gate Logic
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998
4 Input NAND in CPL
Introduction to VLSI Design
Introduction
© Steven P. Levitan 1998