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RFID Secure Credit Card 18-525 Project Proposal (M4) Giovanni Fonseca David Fu Amir R. Ahmad Ghiti Stephen Roos Status • We are currently in the process of acquiring and writing Verilog descriptions of the various components of our design • To Do: – Further specify design components – Decide whether to implement Anti-collision and Anti-tearing blocks – Specify the encryption algorithm to be used Project Proposal • We plan to implement a secure RFID credit card microprocessor • The processor will use encrypted communications with CRC checks and Challenge/Response sequences • The device will conform to current RFID and credit card security standards Major Functional Blocks • Control Block – Coordinates operation of the microprocessor, memory, and encryption modules – Registers • Input (32-bits, 384 trans) • Output (32-bits, 384 trans) • CRC (16-bits, 220 trans) – Logic • Challenge/Response Block (32-bits, 20K trans) • Misc Control Logic (2K trans) • Total: ~23K transistors General Algorithm • • • • • • • Power On Reset Host Challenge/Response Card Challenge/Response Payload Transmission Password Recycle Verification Signal Transaction Committal Design Decisions • We decided to implement the card side of the technology rather than the host side because of the high complexity of the host side • We are using a challenge/response token security system to verify the validity of the host and the card user • We decided to use rotating keys to prevent data capture/spoofing exploits Problems & Questions • What kind of encryption should we use for the challenge/response algorithm? • How should we control the operation of the EEPROM? • Should we implement anti-tearing and/or anticollision?