Download Slides 4 - USC Upstate: Faculty

SCSC 311 Information Systems:
hardware and software
Objectives
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU registers
Enhancing CPU performance
The limitations of semiconductor-based microprocessors
Review: CPU Components
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Control unit
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Arithmetic logic unit (ALU)
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Moves data and instructions between main
memory and registers
Performs computation and comparison operations
Set of registers
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Storage locations that hold inputs and outputs for
the ALU
A complex chain of events occurs when CPU executes a program.
Actions Performed by CPU
Fetch cycle Control Unit:
1.
Fetches an instruction from primary storage
(instruction 2. Increments instruction pointer to location of next
cycle)
instruction
3.
Decode: Separates instruction into components
(instruction code and data inputs)
4.
Stores each component in a separate register
Execution
cycle
ALU:
1.
Retrieves instruction code from a register
2.
Retrieves data inputs from registers
3.
Passes data inputs through internal circuits to
perform data transformation
4.
Stores results in a register
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
Instructions and Instruction Sets
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Instruction
 Is lowest-level command to the CPU
 A bit string, logically divided into components (op code and
operands)
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Op code: is the unique binary number represents a instruction
Operands: the input values for the instruction (data or address)
Instruction sets is a collection of instructions that a CPU can process
 Vary among different CPUs
Three types of instruction
 data movement
 data transformation
 sequence control
Three types of instructions
Data Movement Instructions
1.
Copy data among registers, primary storage,
secondary storage, and I/O devices
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Load: data transfer from RAM to a register
Store: data transfer from a register to RAM
Data Transformation Instructions
2.
(details later)
Boolean operations (NOT, AND, OR, XOR)
Addition (ADD)
Bit manipulation (SHIFT)
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Logical shift
Arithmetic shift
Three types of instructions
Sequence control instructions alter the flow of
instruction execution
3.
Branch instruction
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Normally the control unit fetches the next sequential instruction from
RAM at the end of each execution cycle;
Q: how would the control unit accomplish this?
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Ans: In Branch instruction, one operand contains the RAM address for
the next instruction is loaded into PC register
Unconditional branch always depart from the normal sequential
execution sequence
Conditional branch depart from the normal sequential execution
sequence only if a specific condition is met

The control unit checks a register which contains the result
from a Boolean operation
Halt instruction suspends the flow of instruction execution
in the current program.
Q: what happens when an executing program halt?
Six Data Transformation Instructions
• The rules of NOT, AND, OR, XOR, ADD
• ADD
• SHIFT (next slide)
(self-study)
SHIFT Instruction
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Two types of SHIFT instruction
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Logic SHIFT and Arithmetic SHIFT
Logic SHIFT
Q: What can a logic SHIFT instruction do?
Logical SHIFT
Ans: A logic SHIFT instruction can extract a signal bit from a bit string.
 E.g. 1, extract the fourth bit and put this bit on the rightmost
 E.g. 2, extract and check the sign bit of a 2’s complement number
Arithmetic SHIFT
Arithmetic SHIFT instructions perform multiplication or division.
• For unsigned binary numbers: e.g.1: multiple by 2, e.g.2: divided by
four
• For 2’s complement numbers: need to preserve the sign bit first
Complex Processing Operations
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Complex processing operations can be
implemented by combining the primitive
instructions
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Examples …
Most CPUs provide a much larger instruction set
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Directly support complex instructions, such as
multiplication, division, …
Q: Why include these complex instructions in CPU
instruction set?
Complex Processing Operations
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Ans: Tradeoff of CPU design
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Tradeoff between CPU complexity and programming simplicity
 directly support complex instruction complicates circuitry but
reduces programming complexity
Tradeoff between CPU complexity and program execution speed
 multi-step instruction sequences execute faster if they are
executed within hardware as a single instruction – avoiding
overhead
Note that: additional instructions are required when new data
types are added
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E.g., If double precision floating point data type are supported by
CPU, a set of instructions are required for this data type
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
Instruction Format
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Instruction format is a template
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specifies the number of operands
specifies the position and length of the op code and
operand(s)
Since instructions vary in the number and type of operands,
CPUs support multiple instruction formats (in the next slide)
Instruction formats vary among CPUs:
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op code size
meaning of specific op code
length and coding format of operand
Etc. ...
(1) A 20-bit instruction
uses register inputs
and output:
8-bit Op code, 3 4-bit
operands store
register numbers
(2) A 32-bit load and
store instruction:
8-bit Op code, 2 4bit operands, 1 16bit operand
Fixed Length Instruction vs.
Variable Length Instruction
Fixed length
Instructions
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Padding shorter instructions with trailing zeros
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Simplify the instruction fetching
inefficient memory use
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Variable
length
Instructions
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(why?)
Complicate the instruction fetching (why?)
efficient memory use
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
Complex Instruction Set Computing
(CISC)
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CISC
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In early days, memory is expensive, slow
CPU designer provided complex instructions
do more work per instruction  each complex instruction require
less memory and execution time
Features of CISC
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Need less memory for program storage and execution
Complex instructions usually have variable instruction length
A large instruction set complicates CPU design  CISC CPUs
are complicated  hard to manufacture
Reduced Instruction Set Computing
(RISC)
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RISC is a relatively new philosophy of CPU design
(1980s - )
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Absence of some complex instructions from the instruction set
 RISC CPUs do not combine data transformation and data
movement in one instruction
RISC uses fixed length instructions, short instruction length, large
number of general-purpose registers
Feature of RISC
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Need more memory for program storage and execution
Inefficient at executing complex instructions
RISC CPU is simple, easy to manufacture
RISC vs. CISC
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RISC vs. CISC
 OSs are implemented based on CPU design
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RISC chip: e.g. Hewlett Packard's PA-RISC processor
Apples’ power Macintosh and some version of Linux are
implemented based on RISC processor
CISC chip : e.g. Intel Pentium, Xeon, Itanium
Win OS are implemented based on CISC processor
Pros and Cons of CISC and RISC
e.g. c = a * b
Q 1: Which CPU design is better ?
Q 2: Why does Intel use CISC design?
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
CPU Registers
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Two primary roles of registers
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general-purpose registers: hold data for currently executing
program that is needed quickly or frequently
special-purpose registers: store information about currently
executing program and status of CPU
General-Purpose Registers
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General-purpose registers hold intermediate
results and frequently needed data items
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like a scratch-pad for CPU
Used only by currently executing program
Implemented within the CPU, so that contents can
be read or written quickly
Increasing general-purpose registers usually
decreases program execution time, to a point
Q: Why is that?
Special-Purpose Registers
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CPU uses special-purpose registers to track processor
and program status
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Some special purpose registers
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Instruction register
Instruction pointer (a.k.a. program counter)
Program status word (PSW)
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each bit in PSW is called a flag
At the end of each execution cycle, control unit tests PSW
flags to determine whether an error has occurred.
Examples of PSW bits …
Word Size
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A word is a unit of data that contains a fixed number of bits.
 the amount of data that a CPU processes at a time
 32-bit CPU, 64-bit CPU
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Word size
 matches the size of general purpose registers
 is a fundamental CPU design decision
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Implications for system bus design and implementation of RAM
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the bus width should be at least as large as word size
RAM should be able to read / write a word at a time
Increasing word size usually increases CPU efficiency, up to a
point
Q: why is that?
E.g.,: Doubling word size generally increases the number of CPU
components by 2.5 to 3 times
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU Registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
Clock Rate
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System clock
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A digital circuit that generates timing pulses (ticks) and
transmits the pulses to other components
All devices coordinate their activities with the system clock.
The clock rate: the frequency at which the system clock
generates timing pulses, measured in MHz or GHz
The CPU cycle time – inverse of clock rate, measured in
nanosecond
Q: A computer has clock rate 5 GHz, what is CPU cycle
time?
Clock Rate
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The clock rate / cycle time is only a part of CPU performance
measurement
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The rate of actual / average instruction execution is measured in MIPS
or MFLOPS
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Simple instructions need one cycle time
Complex instructions usually need multiple cycle time
CPU relies on slower devices (RAM or HD) for supply of data
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The performance of a computer system is not only decided by the CPU,
but also by other devices (RAM, system bus … )
Example …
Wait state: each clock cycle that the CPU spends waiting for a slower
device
Q: How to enhance the performance of a computer system ?
Enhancing Processor Performance
Memory caching
(in Ch 5)
Pipelining
Method of organizing CPU circuitry to
enable multiple instructions to execute
simultaneously in different stages
Branch prediction
and speculative
execution
Ensure pipeline is kept full while
executing conditional branch
instructions
Multiprocessing
Duplicate CPUs or processor stages
execute in parallel
Pipelining
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Basic observation: each step in fetch and execution cycle is
performed by a separate portion or stage of the CPU circuitry.
1.
Fetch
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Increment IP
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Decode
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Access ALU inputs
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Execute arithmetic / comparison
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Store ALU output
Pipelining
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Organizing CPU circuitry to enable multiple instructions to be in different
stages of execution at the same time.
Similar to an assembly line
Challenges in Pipelining
It is difficult to fully realize the theoretical
improvement of pipelining
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hard to design a CPU that finishes different stages in
one clock cycle.
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Some instructions in a program are not executed
sequentially.
 Conditional branch – CPU does not know which
branch to take until evaluate a condition  has to
break the pipelining
Branch prediction and speculative execution
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Some solutions to the problem of conditional branch in pipelining
 Early evaluation
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Branch prediction
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CPU gets several instructions ahead of the current one, exam
whether there is conditional branch instruction, if so, try to evaluate
the conditional branch instruction earlier.
But not always possible
CPU guesses which branch to take based on past experience
(maybe CPU executed this portion of code before)
Cannot guarantee taking the correct path
Simultaneous execution
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CPU executes both paths until the condition branch is evaluated,
then aborts the incorrect path
Requires redundant CPU stages and registers
Multiprocessing
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Multiprocessing: CPU architecture duplicates
CPUs or processor stages can execute in
parallel.
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Some approaches of multiprocessing:
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Duplicate circuitry for some or all processing stages within a
single CPU (80’s)
e.g. Sun UltraSparc CPU duplicates ALU, Registers
Embedding multiple CPUs in a computer system and sharing
memory (90’s)
Multiple CPUs to be placed on the same chip and sharing
memory
 Enable multiple CPUs communicate at higher speed (2000 -)
Index
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CPU execution cycle
CPU instructions
Instruction format
CPU design: CISC vs. RISC
CPU Registers
Enhancing CPU performance
The limitations of semiconductor-based
microprocessors
The Physical CPU
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CPU is a complex system
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Contains millions of switches, which perform basic
processing functions
From early CPUs with hundreds of switches to modern
CPUs with millions of switches
The physical implementation of CPUs
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Switches and Gates
Are basic building blocks of computer processing
circuits
Switches and Gates
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Electronic switches
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Control electrical current flow in a circuit
Implemented as transistors
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Gates
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a solid state semiconductor device
control the flow of electronic current
An interconnection of switches
A circuit that can perform a processing function on an
individual binary electrical signal, or bit
The construction of switches and the properties of
electricity determine the CPU’s speed and reliability.
(The symbols of gates are not required.)
Addition circuit: combines a half-adder and an array of full adders
(The detailed layout is not required.)
Electrical Properties of switches and Gates
Conductivity
Ability of an element to enable electron flow
(conductor)
Resistance
Loss of electrical power that occurs within a conductor
(electrical energy  heat and/or light)
Heat
Two negative effects of heat:
 Physical damage to conductor
 Changes to inherent resistance of conductor
Dissipate heat with a heat sink, fan
Speed and
circuit length
Time required to perform a processing operation is a function
of length of circuit and speed of light
Miniaturization: reduce circuit length for faster processing
Processor Fabrication
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Performance and reliability of processors has
increased with improvements in materials and
fabrication techniques
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Transistors and integrated circuits (ICs)
Microchips and microprocessors
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First microprocessor (1971) 2,300 transistor
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Current memory chip – 300 million
transistors
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Small circuit size, low-resistance materials,
and heat dissipation ensure fast and reliable
operation
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Fabricated using expensive processes etching process (details are not required)
Current Technology Capabilities and
Limitations
Moore’s Law: rate of increase in transistor density on microchips
doubles every 18-24 months with no increase in unit Cost
Current Technology Capabilities and
Limitations
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Rock’s Law
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Arthur Rock made a short addendum to Moore’s
Law
Cost of fabrication facilities for the latest chip
generation doubles every four years
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E.g., A fabrication facility using latest production
processes costs at least $10 B.
Q1: Does Rock’s Law mean CPUs are becoming more expensive?
Q2: Would Moore’s Law always be true?
Future Trends
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Semiconductors are approaching fundamental physical
size limits
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Further miniaturization will be more difficult to achieve
 The nature of etching process
 The limits of semiconducting materials
Some technologies may improve performance beyond
semiconductor limitations (details are not required)
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Optical processing
Hybrid optical-electrical processing
Quantum processing