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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 23: November 2, 2012 Pass Transistor Logic: part 2 (Cascading without Buffers) 1 Penn ESE370 Fall2012 -- DeHon Previously 2 Penn ESE370 Fall2012 -- DeHon Two XOR Gates 3 Penn ESE370 Fall2012 -- DeHon Today • Pass Transistor Circuit – Output levels – Cascading • Series pass transistors? • Delay • Transmission gates • Tristate gates 4 Penn ESE370 Fall2012 -- DeHon Cascading Pass Transistors 5 Penn ESE370 Fall2012 -- DeHon Chain without Inverters • What if we did this? 6 Penn ESE370 Fall2012 -- DeHon Extract key path 7 Penn ESE370 Fall2012 -- DeHon t=0 (after Vin transition 10) 8 Penn ESE370 Fall2012 -- DeHon t=4t (after Vin transition 10) 9 Penn ESE370 Fall2012 -- DeHon t=∞ (after Vin transition 10) 10 Penn ESE370 Fall2012 -- DeHon Focus on Pass tr • Vgs? • Operation mode? • Current flow? 11 Penn ESE370 Fall2012 -- DeHon Voltage of Chain • What is voltage at output? 12 Penn ESE370 Fall2012 -- DeHon How compare • Compare 13 Penn ESE370 Fall2012 -- DeHon DC Analysis 14 Penn ESE370 Fall2012 -- DeHon DC Analysis – chain of 6 15 Penn ESE370 Fall2012 -- DeHon Conclude • Can chain any number of pass transistors and only drop a single Vth 16 Penn ESE370 Fall2012 -- DeHon Transient 17 Penn ESE370 Fall2012 -- DeHon Closeup 18 Penn ESE370 Fall2012 -- DeHon Capacitance • What is Capacitance per stage (@y)? 19 Penn ESE370 Fall2012 -- DeHon Delay • Delay as a function of chain length? 20 Penn ESE370 Fall2012 -- DeHon Compare • CMOS • Buffered Pass TR • Unbuffered Pass TR • Delay • Area 21 Penn ESE370 Fall2012 -- DeHon Pass TR Tree • What if we did this? 22 Penn ESE370 Fall2012 -- DeHon Path • What’s different about this? 23 Penn ESE370 Fall2012 -- DeHon Gate Cascade? • What are voltages? 24 Penn ESE370 Fall2012 -- DeHon Demonstration Circuit 25 Penn ESE370 Fall2012 -- DeHon SPICE • TODO show spice results of voltages 26 Penn ESE370 Fall2012 -- DeHon Demonstration Chain 27 Penn ESE370 Fall2012 -- DeHon Spice 28 Penn ESE370 Fall2012 -- DeHon Conclude • Cannot cascade degraded inputs into gates. 29 Penn ESE370 Fall2012 -- DeHon Midterm 2 Topics • Tau-model – Estimation and optimization • Elmore-delay – Estimation and optimization • Energy and power – Estimation and optimization – Dynamic and static • Logic – CMOS – Ratioed – Pass transistor • Scaling • Noise Margins • No clocking – Except to motivate delay targets and power calculations Note: 2010 midterm and 2011 midterm2 30 Penn ESE370 Fall2012 -- DeHon Time Permitting… 31 Penn ESE370 Fall2012 -- DeHon Other Gates 32 Penn ESE370 Fall2012 -- DeHon Other gates • What does this do? B A More examples in book. 33 Penn ESE370 Fall2012 -- DeHon Pass Rail-to-Rail 34 Penn ESE370 Fall2012 -- DeHon Transmission Gate • Voltage levels at output? 35 Penn ESE370 Fall2012 -- DeHon Bus Drivers 36 Penn ESE370 Fall2012 -- DeHon Tristate Driver 37 Penn ESE370 Fall2012 -- DeHon Tri-State Drivers 38 Penn ESE370 Fall2012 -- DeHon Idea • There are other circuit disciplines • Can use pass transistors for logic – Even chains of pass transistors – Sometimes gives area or delay win • Do not cascade as easily as CMOS 39 Penn ESE370 Fall2012 -- DeHon Admin • Project – Due Saturday • Daylight Savings Time change this weekend – …get an extra hour to study for… • Midterm 2: Nov. 7th – Evening Wednesday 40 Penn ESE370 Fall2012 -- DeHon
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