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Active Pixel Sensors in high-voltage CMOS
technologies for ATLAS
Ivan Perić
University of Heidelberg, Germany
Ivan Peric, WIT 2012
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Introduction:
High-Voltage CMOS Pixel Detectors
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HV CMOS detectors
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High-voltage particle detectors in standard CMOS technologies (or “smart diode
arrays” - SDAs) are a new detector family that allows implementation of low-cost
radiation-tolerant detectors with good time resolution.
The deep n-well in a p-substrate is used as the charge-collecting electrode
The entire CMOS pixel electronics are placed inside the deep n-well. PMOS
transistors are placed directly inside the deep n-well, NMOS transistors are situated
in their p-wells that are embedded in the deep n-well as well.
A typical reverse bias voltage is 60 V and the depleted region depth ~15 m. Signal
charge collection occurs mainly by drift.
2.5µm
Input of the amplifier
The use of a high
voltage technology is
not mandatory for the
concept .
A SDA structure has
been also implemented
in a low-voltage 65 nm
technology
Pixel size is 2.5µm!
Ivan Peric, WIT 2012
Transistors
Deep n-well
SDA detector
N-well contact
Depleted p-substrate
between and underneath
n-wells (white area)
Nine pixels of the SDAbased pixel detector
implemented in 65nm
CMOS technology.
3D presentation of the real
layout.
HV CMOS detectors
Pixel
“Smart” Diode
n-Well
Drift
Potential energy (e-)
~15µm
Depletion zone
P-Substrate
“Smart diode” array
The third dimension illustrates electron potential energy.
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Strong points
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1) Active sensor
2) CMOS in-pixel electronics – “intelligent “detectors.
3) Fast signal collection
– ~15μm drift path, 50V
4) Thinning possible
– Since the charge collection is limited to the chip surface, the sensors can be thinned.
5) Price and technology availability
– Standard (HV) technology without any adjustment is used
– Many industry relevant applications of HV CMOS technologies assure their long tern
availability.
– 180nm technology: 160k€ and 1.5k€/8 inch wafer (1 wafer ~ 200 cm2)
– The structure can be also implemented in many low voltage technologies.
6) High tolerance to non-ionizing radiation damage
– High drift speed
– Short drift path
7) High tolerance to ionizing radiation
– Deep submicron technology
– Radiation tolerant design can be used.
– PMOS transistors, that are more tolerant to radiation, can be used as well in contrast to
standard MAPS.
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Capacitive Coupled Pixel Detectors
- CCPDs
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CCPD
Pixel
Readout chip
Glue
Smart diode- or fully-depleted sensor
Signal charge
The signal from sensor chip is transmitted capacitively to the readout chip.
The sensor and readout chips are flipped and glued .
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CCPD – test chip
Monolithic matrix
CCPD matrix (sensor)
Electrodes for capacitive transmission
CCPD matrix (readout)
Sensor and readout matrix implemented as same design (to save costs)
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CCPD - test system
wire bonds
Chip A
Sensor pixels
chips
Signal transmission
PCBA
Chip B
Sensor pixels
PCBB
Readout pixels
Sensor electrode
E-field
Readout electrode
Readout pixels
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High-Voltage CMOS Detectors for ATLAS
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CCPD Concept
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CCPD for ATLAS pixel detector
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Replacing the passive diode-based pixel sensor with an “intelligent” pixel sensor
implemented in HV CMOS technology.
Intelligence: the pixels are able to distinguish a signal from the background and to
respond to a particle hit by generating an address information.
Pixel readout chip (FE-chip)
Pixel electronics based on charge sensitive amplifier
Bump-bond pad
Bump-bond
Pixel length = 250 μm
Pixel sensor
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CCPD for ATLAS pixel detector
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The HVCMOS sensor pixels are smaller than the standard ATLAS pixels, for instance
25μm x 125μm - so that several such pixels cover the area of the original pixel.
The HV pixels contain low-power (~5 μW) CMOS electronics based on a charge
sensitive amplifier and a comparator.
Pixel readout chip (FE-chip)
Pixel electronics based on charge sensitive amplifier
Coupling
capacitance
Bump-bond pad
Glue
Transmitting
plate
Pixel CMOS sensor
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Summing line
62.5 or 125 μm
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CCPD for ATLAS pixel detector
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The electronics responds to a particle hit by generating a pulse.
The signals of a few pixels are summed, converted to voltage and transmitted to the
charge sensitive amplifier in the corresponding channel of the FE chip using AC
coupling.
For comparison and testing purposes, the signal transmission can – in addition to
capacitive coupling – also be established by classical bump-bonding.
Pixel readout chip (FE-chip)
Pixel electronics based on charge sensitive amplifier
Coupling
capacitance
Bump-bond pad
Glue
Transmitting
plate
Pixel CMOS sensor
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Summing line
62.5 or 125 μm
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CCPD for ATLAS pixel detector
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Each of the pixels that couple to one FE receiver can have its unique signal
amplitude, so that the pixel can be identified by examining the amplitude information
generated in FE chip.
In this way, spatial resolution in - and z-direction can be improved.
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Module concept
-We plan to design multi-reticle modules.
-We do not need electrical connections between reticles
-The guard rings at the reticle edge s shouldn‘t lead to
insensitivities.
-The charge is collected from substrate to nearest pixels.
Relicle
Sensor1
Guard rings <100µm
Relicle
Sensor1
Sensor1
Module position in detector
Sensor2
Sensor
Wire bonds for sensor
Pixel
Guard ring
FE chip
PCB
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Wire bonds for FE chips
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Advantages compared to existing detectors
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No need for bump-bond connection between the sensor and readout chip – lower
price, better mechanical stability, less material
Commercial sensor technology – lower price
No need for bias voltages higher than 60V
Operation at temperatures above 0C is according to tests possible (irradiations to
1015 neq/cm2)
Increased spatial resolution (e.g. 25m x 125m binary resolution) with the existing
FE chip
Smaller clusters at high incidence angles
Possibility of sensor-thinning without signal loss. Since we do not use bumps and FE
chips can be thinned as well, the amount of material would be very low.
Interesting choice for other experiments where low-mass detectors are needed such
as CLIC, ILC, CBM, etc...
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Strip-like Concept
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Pixel detector compatible to strip-readout electronics
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Present LHC strip detectors consist of large-area strip sensors that are connected by
wire bonds to multi-channel ASICs.
Readout ASIC (such as ABCN)
Comparator or ADC
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CSA
Wire-bonds
Strip sensor
Strip
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Pixel detector compatible to strip-readout electronics
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We replace a strip with a line of pixels in HVCMOS technology.
Readout ASIC (such as ABCN)
Comparator or ADC
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Wire-bonds
Pixels
CMOS sensor
CSA
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Pixel detector compatible to strip-readout electronics
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Every pixel generates a digital pulse with unique amplitude of logic one.
The pixel outputs are summed, converted to voltage signal and transmitted to readout
ASIC.
Summing line
Readout ASIC (such as ABCN)
Comparator or ADC
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Wire-bonds
Pixels
CMOS sensor
CSA
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Pixel detector compatible to strip-readout electronics
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A large area CMOS sensor can be produced by stitching several 2cm x 2cm wafer
reticles.
Any arbitrary pixel group pattern is possible.
Advantages:
Commercial sensor technology – lower price per unit area
Intrinsic 2D spatial resolution (e.g. 25 m x 125 m binary resolution)
No need for bias voltages higher than 60V
Operation at temperatures above 0C is according to tests possible (irradiations to
1015 neq/cm2)
Thinning possible
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Simultaneous readout from two 2D sensitive layers
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Simultaneous readout from two 2D sensitive layers. Signals from two sensor layers
can be easily combined in a single readout ASIC.
CSA
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Comparator or ADC
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Test Chip HV2FEI4
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HV2FEI4
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Pixel matrix: 60x24 pixels
Pixel size 33 m x 125 m
21 IO pads at the lower side for
CCPD operation
40 strip-readout pads (100 m pitch)
at the lower side and 22 IO pads at
the upper side for strip-operation
Pixel contains charge sensitive
amplifier, comparator and tune DAC
We have received the chips last
week – first results very soon.
IO pads for strip operation
Pixel matrix
4.4mm
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Strip pads
IO pads for CCPD operation
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Pixel electronics
Amplifier
CCPD electrode
G
SFOut
Filter
Comparator
(CR filter)
A
D
Cap. Injection
Output stage
In<0:3>
RW
G
D
G
Select
4-bit DAC
CCPD bus
Programmable current
Strip bus
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CCPD Operation
FEI4 Pixels
Signal transmitted capacitively
CCPD Pixels
Bias A
2
2
Bias B
3
3
Bias C
1
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6 Pixels – Layout
Electrode
Digital part
Tune DAC
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Amplifier
Test setup
HVCMOS
FEI4
PCB
PCB
HVCMOS
FEI4
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Experimental Results with other Prototypes
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Efficiency and Signal Amplitude
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Rolling Shutter Detector
LVDS digital I/Os
Single ramp
ADC
Analog pads
ADC channel
Pixel matrix
2.7 mm
2-stage
switched
capacitor
difference
amplifier
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Test-beam results
Spatial resolution
Sigma: 3.823m
Telescope resolution of 2.3m
is not subtracted
Y pixel
Efficiency vs pixel xy-coordinates
(Mean value = 0.9761)
X pixel
Ivan Peric, WIT 2012
Seed pixel SNR = 27
number of signals
Seed pixel SNR
SNR
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Signal Measurements
3250
55
3000
60
Na
Co
MIPs
2750
Single pixel signal
1200 e
Most probable signal [e]
2500
2250
Cluster signal
2000 e
2000
1750
1500
1250
1000
750
500
250
0
1
2
3
4
5
6
7
Number of pixels
High energy particle signals depending on number of pixels in
cluster.
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CCPD Operation
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CCPD2 detector - photograph
Power supply
and cont. signals
for the readout chip
1.5 mm
Power supply
and cont. signals
for the sensor
Readout chip (CAPPIX)
Sensor chip (CAPSENSE)
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Noise measurement and efficiency
Response probability of all pixels in the matrix
to test pulses that generate from 0 to 2000
electrons
Threshold scan used to measure noise –
noise 23e
100% above ~300e
Response probability
Fit: Mean = 271e Sigma = 23e
1.0
1.0
0.8
0.8
Response probability
Efficiency
Efficiency - window 800ns
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0
500
1000
Signal [e]
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1500
2000
220
240
260
280
300
320
340
360
380
Signal [e]
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Radiation Tolerance
(CCPD2 Sensor)
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Irradiation with protons (1015 neq/cm2, 300 MRad)
55Fe
spectrum and RMS noise
Not irradiated
Room temperature
1.0
RMS Noise 12 e
RMS Noise 0.5mv (12e)
Fe 70mV (1660e)
Room temperature
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55Fe
spectrum and RMS noise
Irradiated
20C
1.0
RMS Noise 270 e
0.8
~number of signals
~ number of signals
0.8
RMS Noise, 13mv (270e)
Fe, 80mV (1660e)
Temperature 20C
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Irradiated with protons to 10 neq
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0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0.00
0.02
0.04
0.06
0.08
0.10
0.00
0.02
0.04
signal amplitude [V]
0.06
0.08
0.12
signal amplitude [V]
55Fe
55Fe
spectrum, RMS noise
Irradiated
10C
RMS Noise
77 e
1.0
RMS Noise, 2.8mv (77e)
Fe, 60mV (1660e)
Temperature 10C
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Irradiated with protons to 10 neq
RMS Noise, 2.4mv (40e)
Fe, 100mV (1660e)
Temperature -10C
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Irradiated with protons to 10 neq
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55
1.0
spectrum, RMS noise
Irradiated
-10C
RMS Noise 40 e
0.8
~number of signals
0.8
~number of signals
0.10
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0.00
0.02
0.04
0.06
signal amplitude [V]
Ivan Peric, WIT 2012
0.08
0.10
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
signal amplitude [V]
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Time Resolution
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Mu3e Detector
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Mu3e experiment at PSI (study of the lepton flavor violating decay mu -> eee)
Proposed: four layers of pixels ~ 80x80m2 size – monolithic pixel detector in HVCMOS
technology
Time stamping with < 100ns resolution required to reduce the number of tracks in an image.
Sensors will be thinned to ~50 m
Thinned chips
Triggerless readout
250 pixel rows
(80 μm pitch)
2cm
Kapton PCB
1cm
~125 pixel rows
(80 μm pitch)
Pixels – active region
~0.3 – 0.5 mm
EoC logic
The figure shows one reticle
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Mu3e Detector
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More details can be seen in poster session:
Dirk Wiedner: “A tracker for the novel mu3e experiment based on high voltage
monolithic active pixel sensors”
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Mu3e Test Chip in 180nm Technology
39m
1.8mm
42x36 pixels
30m
Analog pixels
Digital channels
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0.7m
2 metal layers
Analog pixel layout
Pixel detector chip with CMOS pixel (42x40 pixels) matrix
Pixel size 39x30 micrometers
Separated digital and analog block
Signal time measurements possible
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Collection time measurement
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Charge collection time – IR laser, comparison with the fast capacitive
injection.
No measurable delay versus the capacitive test pulse.
Test pulse
IR laser - 850nm
0.810
0.810
0.805
0.805
Threshold[V]
Threshold[V]
Test pulse
IR laser - 850nm
0.800
0.795
0.790
0.800
0.795
0.790
0
20
40
60
80
Delay time[ns]
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100
120
140
0
1000
2000
3000
4000
5000
Time[ns]
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Time walk measurement
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In-time efficiency vs. signal amplitude (40ns time window)
Detection of signals > 1230 e with 40ns time resolution possible.
Power consumption of the pixel 7.5µm.
B
40ns window
1.0
Efficiency
0.8
0.6
0.4
0.2
0.0
0
1000
2000
3000
4000
5000
6000
Signal[e]
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Pixel detector in 65nm technology
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Pixel size - 2.5µm
55Fe measurement
Shadow of 16m thick golden bonding wire
255
0.5000
250
16µm
245
240
1.500
235
2.500
230
3.500
Pixel Zeile
225
220
4.500
215
5.500
210
205
200
195
190
185
180
175
5
10
15
20
25
30
Pixel Spalte
Pixel matrix (32x256)
Pixel
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Experimental results - overview
HVPixel1 – CMOS in-pixel electronics with hit detection
Binary RO
Pixel size 55x55μm
Noise 60e
MIP seed pixel signal 1800 e
Time resolution 200ns
Capacitive coupled hybrid detector
CCPD2 -capacitive coupled pixel detector
Pixel size 50x50μm
Noise 30-40e
Time resolution 300ns
MIP SNR 45-60
Irradiations of test pixels
60MRad – MIP SNR 22 at 10C (CCPD1)
1015neq MIP SNR 50 at 10C (CCPD2)
HV2FEI4 chip (first test next week!!!)
CCPD for ATLAS pixel detector
Readout with FEI4 chip
Reduced pixel size: 33x125μm
RO type: capacitive and strip like
3 pixels connected to one FEI channel
Monolithic detector –
continuous readout
with time measurement
MuPixel –
Monolithic pixel sensor for
Mu3e experiment at PSI
Charge sensitive amplifier in
pixels
Hit detection, zero suppression
and time measurement at chip
periphery
Pixel size: 39x30 μm (test chip)
(80 x 80 μm required later)
MIP seed signal 1500e (expected)
Noise: ~40 e (measured)
Time resolution < 40ns
Power consumption
7.5µW/pixel
1. Technology 350nm HV – substrate 20 cm uniform
2. Technology 180nm HV – substrate 10 cm uniform
3. Technology 65nm LV – substrate 10 cm/10 m epi
Ivan Peric, WIT 2012
Monolithic detector frame readout
PM2 chip - frame mode readout
Pixel size 21x21μm
4 PMOS pixel electronics
128 on-chip ADCs
Noise: 21e (lab) - 44e (test beam)
MIP signal - cluster: 2000e/seed: 1200e
Test beam: Detection efficiency >98%
Seed Pixel SNR ~ 27
Cluster signal/seed pixel noise ~ 47
Spatial resolution ~ 3.8 m
HPixel - frame mode readout
In-pixel CMOS electronics with CDS
128 on-chip ADCs
Pixel size 25x25 μm
Noise: 60e (preliminary)
MIP signal - cluster: 2100e/seed: 1000e
(expected)
SDS - frame mode readout
Pixel size 2.5x2.5 μm
4 PMOS electronics
Noise: 20e (preliminary)
MIP signal (~1000e - estimation)
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Conclusion
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We have developed a new pixel sensor structure (smart diode array) for high energy
physics that is implemented in high voltage CMOS technologies.
The advantages over conventional silicon sensors include lower cost, lower mass,
lower operating voltage, smaller pitch, and smaller clusters at high incidence angles,
all with comparable radiation hardness.
We have implemented various test structures in 350nm and 180nm technologies and
measured excellent detection and radiation properties.
Measured time resolution < 40ns (IR laser), detection efficiency ~98% (test beam)
Irradiated up to 1015 neq/cm2 and dose 300MRad
We would like to integrate our sensors into existing ATLAS readout systems, for this
we have two concepts:
Capacitive coupled pixel detectors -> readout with pixel readout chips like FEI4
Strip-like sensors -> readout with strip readout AISCs
We have designed a test detector (in 180nm HV CMOS technology) to test the two
concepts – first measurements soon.
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Thank you
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Backup Slides
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HV2FEI4 - Architecture
12x2
Column control
IO pads for strip operation
Matrix
Cap. Injection
SFOut
Test Pad
20x3
Column control
Strip Pads
Bias DACs
IO pads for CCPD operation
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Strip and Test-Operation
Column control SR
Strip bus
R2
R2
L2
L2
R1
R1
L1
L1
R0
R0
L0
L0
Bias A
Pad
Bias B
Pad
Bias C
3
3
SelectL=0
SelectR=0
Row control SR
Mon Pad
33um
125um
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Chip on the sensor concept (CCPD2)
Pixel
Readout chip
Bump for power supply
Smart diode- or fully-depleted sensor
Signal charge
The sensor and readout chips are flipped and connected by a few bumps
Advantage – no need to wire-bond both chips
Power and signals for ROC provided by sensor chip
Edgeless sensor covered with many small ROCs can be made
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CCPD2 – photographs of the chips
CAPPIX
Power and signal bumps
Ivan Peric, WIT 2012
CAPSENSE
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CCPD2 detector - photograph
Power supply
and cont. signals
for the readout chip
1.5 mm
Power supply
and cont. signals
for the sensor
Readout chip (CAPPIX)
Sensor chip (CAPSENSE)
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Collection time measurement
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Digital part
ToT is proportional to collected charge
Does not depend on collection speed
Test signal
Ampl. out
del1
1400e
Window
Comp out
Penetration depth of 850nm light ~14um?
Similar distribution of charge generation as for MIPs?
del2
IR laser signal
N-well
5u m
Ampl. out
10u m
1400e
60%
drift
Comp out
Window
40%
diffusion
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Time walk measurement
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Digital part
Test signal
Test signal
Ampl. out
Ampl. out
Comp out
del1
Comp out
Window
Window
del2
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