Download Embedded DRAM with data retention low

312 Mhz 16-Mb Random Cycle
Embedded DRAM Macro for
Mobile applications
A paper by: Fukashi Morishita, Isamu Hayashi, Hideto Matsuoka, Kazuhiro Takahashi,
Kuniyasu Shigeta,Takayuki Gyohten, Mitsutaka Niiro, Hideyuki Noda, Mako Okamoto, Atsushi Hachisuka,
Atsushi Amo,Hiroki Shinkawata, Tatsuo Kasaoka, Katsumi Dosaka, Kazutami Arimoto, Member, IEEE,
Kazuyasu Fujishima,Kenji Anami, Senior Member, IEEE, and Tsutomu Yoshihara, Member, IEEE
Presented By: Eric Tramel
Features of the Proposed Design
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Self-adjusting Timer Control (STC)
Negative Edge Transmission (NET)
Power-Down Data Retention (PDDR)
Self-adjusting Timer Control (STC)
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Reduces the variance in time delay caused
by Process, Voltage, and Temperature
(PVT) differences between
chips.
Unused during PDDR mode to save on
power
consumption.
Helps achieve stable random-cycle
operation of the DRAM.
Negative Edge Transmission (NET)

Enables long distance signal transmission from
center control blocks to outer local array control
blocks.
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This scheme is needed because single phase, small pulse
width signals get lost in the background for long distance
transmissions, thus restricting our physical design.
Allows for consistent timing in each block and
accurate control signals to each array, despite
varying core capacities.
Transmits control signals as two-phase
asynchronous signals.
Only falling edges controlled by NMOS transistors
are detected in order to ensure consistent timings.
Power-Down Data Retention
(PDDR)

Allows for decreased power consumption by
shutting off non-operating blocks of memory.
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Prevents leakage current and unnecessary
refreshes.
Decreases overall power consumption by
regulating and lowering supply voltages across
the
chip.
Slower chip control timing for non-clock data
retention (and STC shutdown).
Design Factoids
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Bit Size:
Cell Size:

Feature Size:
Die Size:
Power Supply:
1.2V,
2.5V
Error Correction:
Memory Blocks:
Cells Per Row:
Rows per Block:
Cell Construction:
Refresh Time:
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
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
(PDDR)
Bit Line Swing:
Bit Line Bias:
16 Mb
0.42 x 0.84:
0.35μm²
0.13μm
13.98mm²
Vddl =
Vddh =
No
128 Blocks at 128Kb
8
128
MIM, Ta2O5
70ms@80°C,
50ms@80°C
1.2V
None