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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 3: September 3, 2014 Gates from Transistors 1 Penn ESE370 Fall2014 -- DeHon Previously • Simplified models for reasoning about transistor circuits – Zeroth-order 2 Penn ESE370 Fall2014 -- DeHon Today • How to construct static CMOS gates 3 Penn ESE370 Fall2014 -- DeHon Outline • Circuit understanding (preclass) – Gate function identification • Static CMOS – Structure – Inverter – Construct gate – Inverting – Cascading 4 Penn ESE370 Fall2014 -- DeHon Why Zeroth Order Useful? • Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits • Make sure understand logical function (achieve logical function) before worrying about performance details 5 Penn ESE370 Fall2014 -- DeHon What gate? 6 Penn ESE370 Fall2014 -- DeHon What function? 7 Penn ESE370 Fall2014 -- DeHon DeMorgan’s Law • /f = a + b • What is f? 8 Penn ESE370 Fall2014 -- DeHon What function? 9 Penn ESE370 Fall2014 -- DeHon Static CMOS Gate 10 Penn ESE370 Fall2014 -- DeHon Static CMOS Gate Structure 11 Penn ESE370 Fall2014 -- DeHon Static CMOS Gate Structure 12 Penn ESE370 Fall2014 -- DeHon Static CMOS Gate Structure • Drives rail-to-rail – Power rails are Vdd and Gnd – output is Vdd or Gnd • Inputs connects to gates load is capacitive • Once charge capacitive output, doesn’t use energy – (first order) • Output actively driven Penn ESE370 Fall2014 -- DeHon 13 Inverter • Out = /in 14 Penn ESE370 Fall2014 -- DeHon Inverter 15 Penn ESE370 Fall2014 -- DeHon Why zeroth-order adequate? • Static analysis – can ignore capacitors • Capacitive loads – resistances don’t matter • Feed forward for gates – – don’t generally have loops – can work forward from known values • Logic drive to ground or Vdd (rail-to-rail) – Don’t have to reason about intermediate voltage levels 16 Penn ESE370 Fall2014 -- DeHon What zeroth-order not tell us? • Delay • Dynamics • Behavior if not – Capacitively loaded – Acyclic (if there are Loops) – Rail-to-rail drive (voltages between 0 and Vdd) 17 Penn ESE370 Fall2014 -- DeHon Gate Design Example 18 Penn ESE370 Fall2014 -- DeHon Gate Design • Design gate to perform: f=(/a+/b)*/c 19 Penn ESE370 Fall2014 -- DeHon f=(/a+/b)*/c • Strategy: 1. Use static CMOS structure 2. Design PMOS pullup for f 3. Use DeMorgan’s Law to determine /f 4. Design NMOS pulldown for /f 20 Penn ESE370 Fall2014 -- DeHon f=(/a+/b)*/c • PMOS Pullup for f? 21 Penn ESE370 Fall2014 -- DeHon f=(/a+/b)*/c • Use DeMorgan’s Law to determine /f. • What is /f ? 22 Penn ESE370 Fall2014 -- DeHon f=(/a+/b)*/c • NMOS Pulldown for /f? 23 Penn ESE370 Fall2014 -- DeHon f=(/a+/b)*/c a c b 24 Penn ESE370 Fall2014 -- DeHon Static CMOS Source/Drains • With PMOS on top, NMOS on bottom – PMOS source always at top (near Vdd) – NMOS source always at bottom (near Gnd) 25 Penn ESE370 Fall2014 -- DeHon TA Office Hours M, W • Poll for times Monday 5-9pm • Poll for times Wednesday 5-9pm 26 Penn ESE370 Fall2014 -- DeHon Inverting Gate 27 Penn ESE370 Fall2014 -- DeHon Inverting Stage • Each stage of Static CMOS gate is inverting 28 Penn ESE370 Fall2014 -- DeHon How do we buffer? 29 Penn ESE370 Fall2014 -- DeHon How implement OR? 30 Penn ESE370 Fall2014 -- DeHon Cascading Stages 31 Penn ESE370 Fall2014 -- DeHon Stages • Can always cascade “stages” to build more complex gates • Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality – but may not be smallest/fastest/least power 32 Penn ESE370 Fall2014 -- DeHon Implement: f=a*/b • Pullup? • Pulldown? 33 Penn ESE370 Fall2014 -- DeHon f=a*/b 34 Penn ESE370 Fall2014 -- DeHon Course Alum – IBM Jobs • Brian Yavoich <[email protected]> – VLSI SRAM circuit design at IBM – Took this course Fall 2011 – Advertising full-time and summer hardware jobs at IBM 35 Penn ESE370 Fall2014 -- DeHon Big Idea • Systematic construction of any gate from transistors 1. Use static CMOS structure 2. Design PMOS pullup for f 3. Use DeMorgan’s Law to determine /f 4. Design NMOS pulldown for /f Penn ESE370 Fall2014 -- DeHon 36 Admin • Office hours – Ron (TA): Monday and Wednesday, Ketterer – Tuesday: Andre 4:15-5:30pm Levine 270 • Thursday: HW1 due • identify gates; use electric • Friday in Detkin (RCA) Lab – Please read through HW2, Lab1 details – Bring USB drive with you to lab on Friday to store waveforms 37 Penn ESE370 Fall2014 -- DeHon