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Automatic Model Refinement of GmC
Integrators for High-Level Simulations
of Continuous-Time Sigma-Delta
Modulators
Michel Vasilevski
Hassan Aboushady, Marie-Minerve Louërat
Laboratory LIP6 University Pierre and Marie Curie, Paris 6, France
May 2009
Outline
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
M. Vasilevski
Laboratory LIP6, University Paris6
2
Outline
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
M. Vasilevski
Laboratory LIP6, University Paris6
3
System-Level
Motivations : Analog Design Flow
System-Level
Specifications
Simulation
Modify
Parameters
Performance
analysis
OK
Circuit-Level
Specifications
Circuit
Topology
Model
Refinement
Sizing : Manual
Circuit-Level
Sized Netlist
Simulation
Modify
Parameters
M. Vasilevski
Performance
analysis
Circuit OK
Laboratory LIP6, University Paris6
4
Continuous-Time SD Modulator
+
-
Aint
sT
+
-
Aint
sT
1/T
DAC
With Accurate Integrators Model
With Ideal Integrators Model
Aint
H(s) 
sT
M. Vasilevski
(1  s / z1)(1  s / z2)...
H( s)  K
(1  s / p1)(1  s / p2)...
Laboratory LIP6, University Paris6
5
Outline
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
M. Vasilevski
Laboratory LIP6, University Paris6
6
GmC Model Refinement
VDD
VBIAS
GmC ideal
Transfer Function:
VCP
Aint Gm
H(s) 

sT
sC
io
ii
 ii
 io
VBC
VSS
M. Vasilevski
C
C
Laboratory LIP6, University Paris6
7
GmC Non-Idealities
CMOS Process:
0.13 μm
ΣΔ Specifications
GmC Integrator Design Results
BW
200 kHz
I0
7.6 μA
OSR
64
Desired fT
1.36 MHz
Aint (Integrator Gain)
1/3
Simulated fT
1.29 MHz
AΣΔ (Input Amplitude)
-5dB
C
3.6 pF
M. Vasilevski
Laboratory LIP6, University Paris6
8
Simplified GmC Model
[Zele,Allstot,JSSC’96]
1  s / z1
H(s)  K
1  s / p1
Simplified models are not sufficiently accurate
VDD
I0
I0
io
VSS
M. Vasilevski
I0
ii
C
I0
 ii
I0
I0
gm  gds
K
2gds
 io
2gds
p1 
C  4Cgd
C
Laboratory LIP6, University Paris6
gm  gds
z1 
2Cgd
9
Accurate Cascoded GmC Model
VDD
I0
io
I0
I0
ii
I0
I0
I0
 io
 ii
VBC
VSS
C
C
H( s)  K
M. Vasilevski
Laboratory LIP6, University Paris6
(1  s / z1)(1  s / z2)
(1  s / p1)(1  s / p2)
10
Outline
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
M. Vasilevski
Laboratory LIP6, University Paris6
11
System-Level
Characterization Flow : Conventional method
System-Level
Specifications : SNR, BW
GmC Model
A(1  s / z1)(1  s / z2)
K int
1  s / p1)(1  s / p2)
s(T
Simulation
Modify
Aint, OSR
SNR analysis
scaling
OK
GmC Specifications
GmC
Topology
Zeros/Poles
Extraction
Sizing : Manual
Circuit-Level
Sized Netlist
Modify
Parameters
Simulation
Performance
analysis
M. Vasilevski
Circuit OK
Laboratory LIP6, University Paris6
12
Characterization Flow : Full Automation
 SystemC-AMS




C++ based tool.
Fixed step discrete-time System-Level simulator.
Adapted to mixed analog-digital systems modeling.
Ongoing standardization (extension SystemC).
 CAIRO+:




C++ based tool.
Exact Bsim3v3 models are used for transistor sizing.
Small-Signal parameters extraction.
Suited for technology migration.
 Full interoperability.
M. Vasilevski
Laboratory LIP6, University Paris6
13
System-Level
Specifications : SNR, BW
Simulation
Modify
Aint, OSR
C++
SystemC-AMS
Characterization Flow : Proposed Method
GmC Model
A int(f1s  s / z1)(1  s / z2)
K
s(1  s / p1)(1  s / p2)
SNR analysis
scaling
OK
GmC Specifications
GmC
Topology
Zeros/Poles
Sizing : Synthesis
CAIRO+
CAIRO+
Symbolic
expression
Sized Netlist
M. Vasilevski
Small-Signal Parameters
Laboratory LIP6, University Paris6
14
Characterization Flow : Full Automation
Conventional method Proposed method
Difficult Interoperability
System/Circuit Level: Manual
interventions for transfer
function characterization.
Fully compatible system to circuit
level interface: C++ based tools,
SystemC-AMS/CAIRO+.
Simulation-Aided transistor
sizing: Time consuming.
« Knowledge » based sizing:
Using CAIRO+ for accurate
transistor sizing, suited for
technology migration.
M. Vasilevski
Laboratory LIP6, University Paris6
15
Outline
1.Motivations
2.GmC Model Refinement
3.Characterization Flow
4.Results and Application
5.Conclusion
M. Vasilevski
Laboratory LIP6, University Paris6
16
2nd order CT SD in a 0.13 mm CMOS
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz
SD output Power Spectral Density
GmC Frequency Response
SNR=47dB
SNR=68dB
Transistors length: L1=10μm, L3=9 μm
M. Vasilevski
Laboratory LIP6, University Paris6
17
2nd order CT SD in a 0.13 mm CMOS
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz
SD output Power Spectral Density
GmC Frequency Response
SNR=68dB
SNR=68dB
Transistors length: L1=3 μm, L3=0.18 μm
M. Vasilevski
Laboratory LIP6, University Paris6
18
Technology migration : 0.25 μm / 0.13 μm
Specifications: SNR= 60 dB, OSR = 64, BW = 200 kHz/10MHz
SNR=52dB
SNR~68dB
M. Vasilevski
0.25 μm
0.13 μm
BW=200kHz
68.2dB
68.4dB
BW=10MHz
52.1dB
67.3dB
Laboratory LIP6, University Paris6
19
5 - Conclusion
• Automatic refinement of high-level system models based
on:
• Exact symbolic expressions for small signal analysis
• Accurate BSIM3v3 transistor models
• Homogeneous Environment (C++):
• High-Level Simulation => SystemC-AMS
• Circuit synthesis and characterization => CAIRO+
• Proposed method illustrated on the GmC integrator of a
2nd order SD modulator.
M. Vasilevski
Laboratory LIP6, University Paris6
20