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The Arrival of the 64bit CPUs - Itanium
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The Arrival of the 64bit CPUs - Itanium
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What is the Intel® Itanium™ Architecture?
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EPIC (Explicitly Parallel Instruction Computing)
IA - 64
compatibility with the IA-32 instruction set.
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CPU speed 800 MHz , 6.4 GFLOPS
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3 Level Cache
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 On-Die Lv1 128 Kb, Lv2 256 Kb
 Lv3 4 Mb
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264 Address space
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25.4 Million Transistors
The Arrival of the 64bit CPUs - Itanium
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The Arrival of the 64bit CPUs - Itanium
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Data Types
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Integer: 1, 2, 4 and 8 byte(s)
Floating-point single, double and
double-extended formats
Pointers: 8 bytes
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Intel® Itanium™ Instruction Format
[(qp)] mnemonic[.comp1][.comp2] dests = srcs
Simple Instruction
add r1 = r2, r3
Predicated instruction
(p4)add r1 = r2, r3
Instruction with immediate
add r1 = r2, r3, 1
Instruction with completer
cmp.eq p3 = r2, r4
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Memory Organization
defines a single, uniform, linear address space of 264 bytes
 Single space means that both data and instructions share the
same memory range.
 Uniform means that there are no address regions with predefined
functionality.
 Linear means that the address space contains no segments; all
264 bytes are consecutive
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Support 2 byte order: Little-endian and Big-endian
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Instruction Level Parallelism(ILP)
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Enabling the compiler/assembly writer to explicitly indicate
parallelism.
Providing a three-instruction-wide word, called a bundle, that
facilitates parallel processing of instructions.
Providing a large number of registers, enabling using different
registers for different variables and avoiding register contention.
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Instruction Groups
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An instruction group is a set of instructions which do not have
read-after-write or write-after-write dependencies between them
and may execute in parallel.
An instruction group must contain at least one instruction; the
number of instructions in an instruction group is not limited.
Instruction groups are indicated in the code by cycle breaks. An
instruction group may also end dynamically during run-time by a
taken branch.
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Instruction Bundles
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Instruction groups are composed of instructions contained in
bundles.
Each bundle contains three instructions, and a template field, which
are set during code generation, by a compiler, or the assembler.
Template allows the processor to dispatch all three instructions in
parallel.
Bundles are aligned at 16-byte boundaries.
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Registers
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128 General registers
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128 Floating-point registers
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64 Predicate registers
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8 Branch registers
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128 Application registers
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Instruction Pointer (IP) register
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Register Validity
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enable propagating validity/invalidity of
a speculative load result.
Each general register has an a
corresponding NaT (Not a Thing) Bit.
Floating-point registers use a special
instance of pseudo-zero, called NaTVal.
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Branching in the Intel® Itanium™ Architecture
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Relative direct branches, using 21-bit
displacement that is appended to the
instruction pointer of the bundle containing the
branch.
Indirect branches, using 64-bit addresses in the
branch registers.
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Predication
Allowing the processor to execute all possible branch paths in parallel.
2
Instruction 4 (P1)
Instruction 5 (P1)
Instruction 6 (P1)
Instruction 1
Instruction 2
Instruction 3(branch)
3
12
Instruction 7 (P2)
Instruction 8(P2)
Instruction 9 (P2)
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Predication
The compiler rearrange instruction in this order, paring
instruction 4 and 7, 5 and 8 and 6 and 9 for parallel execution.
Instruction 1
Instruction 4 (P1)
Instruction 8(P2)
Instruction 2
Instruction 3(branch) 128 bit long
Instruction 7 (P2) Instruction 5 (P1) instruction
Instruction 6 (P1)
Instruction 9 (P2)
word
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Reduced Memory Access Costs
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Hiding memory latency. This enables the
processor to bring the data in time, and avoid
stalling the processor.
Memory latency is hidden through the use of:
 Data speculation
- the execution of an
operation before its data dependency is
resolved.
 Control speculation
- the execution of an
instruction before its control dependencyis
resolved.
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Hiding Memory Latencies
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speculative loads, error/exception
detection is deferred until final result is
actually required:
If no error/exception is detected the
latency is hidden.
If an error/exception is detected then
memory accesses and dependent
instructions must be redone by an
exception handler.
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Speculative loading
Fetch data before the program needs it, even beyond a branch that hasn't executed.
Instruction 1
Instruction 2
1
2
Speculative loading
5
Instruction 3(branch)
Instruction 4
Instruction 5
Instruction 6
3
4
Instruction 7
Instruction 8(Load data)
Speculative Check
Instruction 9 (Use data)
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Floating Point and Multimedia
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support for single, double, and double-extended IEEE formats.
support for multimedia, or data-parallel applications:
integer data and SIMD computations, similar to the MMX™
technology.
floating-point data and SIMD-FP computations, similar to IA32 Streaming SIMD Extensions.
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Itanium™ Architecture Floating-point Features
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128 floating-point registers
A multiply and accumulate instruction (fma), with four different floating-point
registers for operands (f=a * b + c). This instruction enables performing a multiply
and add in the same number of cycles as one add or multiply instruction.
Load and store to and from memory. You can also load from memory into two
floating-point registers.
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Data transfer between floating-point and general registers.
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Multiple status fields register, enables speculation on floating-point operations.
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Quick conversion from integer to floating-point and vice-versa.
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Rotating floating-point registers.
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Multimedia Support
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Integer multimedia is provided by
defining a set of instructions which
treat the general registers 8x8, 4x16, or
2x32 bit elements, and by providing
specific instructions for operating on
these data elements.
support is semantically compatible
with the MMX™ Technology.
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Chipset
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AL460GX (support 4 CPU),
BS460GX (support 2 CPU)
400 MHz Bus speed
DDR-SDRAM, RAMBUS only
FSB slot support Itanium CPU
Board
10 PCI Slot
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Reference
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http://www.pctechguide.com/02proc3.htm#Itani
um
http://www.sysopt.com/articles/64bit/index.html
http://developer.intel.com/design/ia-64
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Any Question?
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